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e1000e: Fix HW Error on es2lan, ARP capture issue by BMC
Several components to this complex fix. The es2lan cards occasionally gave a "HW Error" especially when forcing speed. Some users also reported that the BMC stole ARP packets. The fixes include setting the proper SW_FW bits to tell the BMC that we're active and not do any un-initialization at all, so the setup routine is largely changed. Signed-off-by: David Graham <david.graham@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
David Graham
Jeff Garzik
parent
de5b3077da
commit
2d9498f369
@ -184,6 +184,7 @@
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#define E1000_SWFW_EEP_SM 0x1
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#define E1000_SWFW_PHY0_SM 0x2
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#define E1000_SWFW_PHY1_SM 0x4
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#define E1000_SWFW_CSR_SM 0x8
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/* Device Control */
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#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
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@ -449,6 +449,8 @@ extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
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extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
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u32 usec_interval, bool *success);
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extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
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extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
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extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
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extern s32 e1000e_check_downshift(struct e1000_hw *hw);
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static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
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@ -41,6 +41,7 @@
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#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
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#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
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#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
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#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
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#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
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#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
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@ -48,6 +49,7 @@
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#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
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#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
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#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
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#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
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#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
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@ -85,6 +87,9 @@
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/* Kumeran Mode Control Register (Page 193, Register 16) */
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#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
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/* Max number of times Kumeran read/write should be validated */
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#define GG82563_MAX_KMRN_RETRY 0x5
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/* Power Management Control Register (Page 193, Register 20) */
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#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
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/* 1=Enable SERDES Electrical Idle */
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@ -270,6 +275,7 @@ static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
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u16 mask;
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mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
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mask |= E1000_SWFW_CSR_SM;
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return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
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}
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@ -286,6 +292,8 @@ static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
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u16 mask;
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mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
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mask |= E1000_SWFW_CSR_SM;
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e1000_release_swfw_sync_80003es2lan(hw, mask);
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}
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@ -410,20 +418,27 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
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u32 page_select;
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u16 temp;
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ret_val = e1000_acquire_phy_80003es2lan(hw);
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if (ret_val)
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return ret_val;
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/* Select Configuration Page */
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if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
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if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
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page_select = GG82563_PHY_PAGE_SELECT;
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else
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} else {
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/*
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* Use Alternative Page Select register to access
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* registers 30 and 31
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*/
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page_select = GG82563_PHY_PAGE_SELECT_ALT;
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}
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temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
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ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
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if (ret_val)
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ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
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if (ret_val) {
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e1000_release_phy_80003es2lan(hw);
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return ret_val;
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}
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/*
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* The "ready" bit in the MDIC register may be incorrectly set
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@ -433,20 +448,21 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
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udelay(200);
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/* ...and verify the command was successful. */
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ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
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ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
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if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
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ret_val = -E1000_ERR_PHY;
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e1000_release_phy_80003es2lan(hw);
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return ret_val;
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}
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udelay(200);
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ret_val = e1000e_read_phy_reg_m88(hw,
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MAX_PHY_REG_ADDRESS & offset,
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data);
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ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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data);
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udelay(200);
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e1000_release_phy_80003es2lan(hw);
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return ret_val;
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}
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@ -467,20 +483,27 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
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u32 page_select;
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u16 temp;
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ret_val = e1000_acquire_phy_80003es2lan(hw);
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if (ret_val)
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return ret_val;
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/* Select Configuration Page */
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if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
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if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
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page_select = GG82563_PHY_PAGE_SELECT;
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else
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} else {
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/*
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* Use Alternative Page Select register to access
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* registers 30 and 31
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*/
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page_select = GG82563_PHY_PAGE_SELECT_ALT;
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}
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temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
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ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
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if (ret_val)
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ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
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if (ret_val) {
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e1000_release_phy_80003es2lan(hw);
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return ret_val;
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}
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/*
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@ -491,18 +514,20 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
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udelay(200);
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/* ...and verify the command was successful. */
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ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
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ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
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if (((u16)offset >> GG82563_PAGE_SHIFT) != temp)
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if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
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e1000_release_phy_80003es2lan(hw);
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return -E1000_ERR_PHY;
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}
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udelay(200);
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ret_val = e1000e_write_phy_reg_m88(hw,
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MAX_PHY_REG_ADDRESS & offset,
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data);
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ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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data);
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udelay(200);
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e1000_release_phy_80003es2lan(hw);
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return ret_val;
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}
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@ -882,10 +907,10 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val;
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u32 ctrl_ext;
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u16 data;
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u32 i = 0;
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u16 data, data2;
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ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
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&data);
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ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
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if (ret_val)
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return ret_val;
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@ -893,8 +918,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
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/* Use 25MHz for both link down and 1000Base-T for Tx clock. */
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data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
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ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
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data);
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ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
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if (ret_val)
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return ret_val;
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@ -954,6 +978,18 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
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if (ret_val)
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return ret_val;
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ret_val = e1000e_read_kmrn_reg(hw,
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E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
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&data);
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if (ret_val)
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return ret_val;
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data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
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ret_val = e1000e_write_kmrn_reg(hw,
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E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
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data);
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if (ret_val)
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return ret_val;
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ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
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if (ret_val)
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return ret_val;
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@ -983,9 +1019,18 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
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if (ret_val)
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return ret_val;
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ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
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if (ret_val)
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return ret_val;
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do {
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ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
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&data);
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if (ret_val)
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return ret_val;
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ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
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&data2);
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if (ret_val)
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return ret_val;
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i++;
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} while ((data != data2) && (i < GG82563_MAX_KMRN_RETRY));
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data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
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ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
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@ -1074,7 +1119,8 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
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{
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s32 ret_val;
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u32 tipg;
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u16 reg_data;
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u32 i = 0;
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u16 reg_data, reg_data2;
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reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
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ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
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@ -1088,9 +1134,16 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
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tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
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ew32(TIPG, tipg);
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ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
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if (ret_val)
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return ret_val;
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do {
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ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
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if (ret_val)
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return ret_val;
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ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
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if (ret_val)
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return ret_val;
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i++;
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} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
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if (duplex == HALF_DUPLEX)
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reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
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@ -1112,8 +1165,9 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
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static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
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{
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s32 ret_val;
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u16 reg_data;
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u16 reg_data, reg_data2;
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u32 tipg;
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u32 i = 0;
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reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
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ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
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@ -1127,9 +1181,16 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
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tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
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ew32(TIPG, tipg);
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ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
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if (ret_val)
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return ret_val;
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do {
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ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
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if (ret_val)
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return ret_val;
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ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
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if (ret_val)
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return ret_val;
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i++;
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} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
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reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
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ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
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@ -116,7 +116,7 @@ s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
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}
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/**
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* e1000_read_phy_reg_mdic - Read MDI control register
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* e1000e_read_phy_reg_mdic - Read MDI control register
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* @hw: pointer to the HW structure
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* @offset: register offset to be read
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* @data: pointer to the read data
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@ -124,7 +124,7 @@ s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
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* Reads the MDI control register in the PHY at offset and stores the
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* information read to data.
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**/
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static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
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s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
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{
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struct e1000_phy_info *phy = &hw->phy;
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u32 i, mdic = 0;
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@ -150,7 +150,7 @@ static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
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* Increasing the time out as testing showed failures with
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* the lower time out
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*/
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for (i = 0; i < 64; i++) {
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for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
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udelay(50);
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mdic = er32(MDIC);
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if (mdic & E1000_MDIC_READY)
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@ -170,14 +170,14 @@ static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
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}
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/**
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* e1000_write_phy_reg_mdic - Write MDI control register
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* e1000e_write_phy_reg_mdic - Write MDI control register
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* @hw: pointer to the HW structure
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* @offset: register offset to write to
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* @data: data to write to register at offset
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*
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* Writes data to MDI control register in the PHY at offset.
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**/
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static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
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s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
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{
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struct e1000_phy_info *phy = &hw->phy;
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u32 i, mdic = 0;
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@ -199,9 +199,13 @@ static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
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ew32(MDIC, mdic);
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/* Poll the ready bit to see if the MDI read completed */
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for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
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udelay(5);
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/*
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* Poll the ready bit to see if the MDI read completed
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* Increasing the time out as testing showed failures with
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* the lower time out
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*/
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for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
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udelay(50);
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mdic = er32(MDIC);
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if (mdic & E1000_MDIC_READY)
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break;
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@ -210,6 +214,10 @@ static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
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hw_dbg(hw, "MDI Write did not complete\n");
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return -E1000_ERR_PHY;
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}
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if (mdic & E1000_MDIC_ERROR) {
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hw_dbg(hw, "MDI Error\n");
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return -E1000_ERR_PHY;
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}
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return 0;
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}
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@ -232,9 +240,8 @@ s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
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if (ret_val)
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return ret_val;
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ret_val = e1000_read_phy_reg_mdic(hw,
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MAX_PHY_REG_ADDRESS & offset,
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data);
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ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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||||
data);
|
||||
|
||||
hw->phy.ops.release_phy(hw);
|
||||
|
||||
@ -258,9 +265,8 @@ s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
ret_val = e1000_write_phy_reg_mdic(hw,
|
||||
MAX_PHY_REG_ADDRESS & offset,
|
||||
data);
|
||||
ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
|
||||
data);
|
||||
|
||||
hw->phy.ops.release_phy(hw);
|
||||
|
||||
@ -286,18 +292,17 @@ s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
|
||||
return ret_val;
|
||||
|
||||
if (offset > MAX_PHY_MULTI_PAGE_REG) {
|
||||
ret_val = e1000_write_phy_reg_mdic(hw,
|
||||
IGP01E1000_PHY_PAGE_SELECT,
|
||||
(u16)offset);
|
||||
ret_val = e1000e_write_phy_reg_mdic(hw,
|
||||
IGP01E1000_PHY_PAGE_SELECT,
|
||||
(u16)offset);
|
||||
if (ret_val) {
|
||||
hw->phy.ops.release_phy(hw);
|
||||
return ret_val;
|
||||
}
|
||||
}
|
||||
|
||||
ret_val = e1000_read_phy_reg_mdic(hw,
|
||||
MAX_PHY_REG_ADDRESS & offset,
|
||||
data);
|
||||
ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
|
||||
data);
|
||||
|
||||
hw->phy.ops.release_phy(hw);
|
||||
|
||||
@ -322,18 +327,17 @@ s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
|
||||
return ret_val;
|
||||
|
||||
if (offset > MAX_PHY_MULTI_PAGE_REG) {
|
||||
ret_val = e1000_write_phy_reg_mdic(hw,
|
||||
IGP01E1000_PHY_PAGE_SELECT,
|
||||
(u16)offset);
|
||||
ret_val = e1000e_write_phy_reg_mdic(hw,
|
||||
IGP01E1000_PHY_PAGE_SELECT,
|
||||
(u16)offset);
|
||||
if (ret_val) {
|
||||
hw->phy.ops.release_phy(hw);
|
||||
return ret_val;
|
||||
}
|
||||
}
|
||||
|
||||
ret_val = e1000_write_phy_reg_mdic(hw,
|
||||
MAX_PHY_REG_ADDRESS & offset,
|
||||
data);
|
||||
ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
|
||||
data);
|
||||
|
||||
hw->phy.ops.release_phy(hw);
|
||||
|
||||
@ -420,7 +424,9 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
|
||||
/* For newer PHYs this bit is downshift enable */
|
||||
if (phy->type == e1000_phy_m88)
|
||||
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
|
||||
|
||||
/*
|
||||
* Options:
|
||||
@ -463,7 +469,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
if (phy->revision < 4) {
|
||||
if ((phy->type == e1000_phy_m88) && (phy->revision < 4)) {
|
||||
/*
|
||||
* Force TX_CLK in the Extended PHY Specific Control Register
|
||||
* to 25MHz clock.
|
||||
@ -518,8 +524,11 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/* Wait 15ms for MAC to configure PHY from NVM settings. */
|
||||
msleep(15);
|
||||
/*
|
||||
* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
|
||||
* timeout issues when LFS is enabled.
|
||||
*/
|
||||
msleep(100);
|
||||
|
||||
/* disable lplu d0 during driver init */
|
||||
ret_val = e1000_set_d0_lplu_state(hw, 0);
|
||||
@ -1152,9 +1161,7 @@ s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
|
||||
|
||||
if (!active) {
|
||||
data &= ~IGP02E1000_PM_D3_LPLU;
|
||||
ret_val = e1e_wphy(hw,
|
||||
IGP02E1000_PHY_POWER_MGMT,
|
||||
data);
|
||||
ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
/*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user