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pinctrl: sh-pfc: r8a7795: Add DRIF support
This patch adds DRIF[0-3] pinmux support for r8a7795 SoC. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Ramesh Shanmugasundaram
Geert Uytterhoeven
parent
d07640f576
commit
2d77583198
@ -1656,6 +1656,221 @@ static const unsigned int canfd1_data_mux[] = {
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CANFD1_TX_MARK, CANFD1_RX_MARK,
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};
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/* - DRIF0 --------------------------------------------------------------- */
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static const unsigned int drif0_ctrl_a_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
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};
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static const unsigned int drif0_ctrl_a_mux[] = {
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RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
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};
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static const unsigned int drif0_data0_a_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 10),
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};
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static const unsigned int drif0_data0_a_mux[] = {
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RIF0_D0_A_MARK,
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};
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static const unsigned int drif0_data1_a_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 7),
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};
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static const unsigned int drif0_data1_a_mux[] = {
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RIF0_D1_A_MARK,
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};
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static const unsigned int drif0_ctrl_b_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
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};
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static const unsigned int drif0_ctrl_b_mux[] = {
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RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
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};
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static const unsigned int drif0_data0_b_pins[] = {
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/* D0 */
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RCAR_GP_PIN(5, 1),
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};
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static const unsigned int drif0_data0_b_mux[] = {
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RIF0_D0_B_MARK,
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};
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static const unsigned int drif0_data1_b_pins[] = {
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/* D1 */
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RCAR_GP_PIN(5, 2),
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};
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static const unsigned int drif0_data1_b_mux[] = {
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RIF0_D1_B_MARK,
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};
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static const unsigned int drif0_ctrl_c_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
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};
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static const unsigned int drif0_ctrl_c_mux[] = {
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RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
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};
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static const unsigned int drif0_data0_c_pins[] = {
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/* D0 */
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RCAR_GP_PIN(5, 13),
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};
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static const unsigned int drif0_data0_c_mux[] = {
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RIF0_D0_C_MARK,
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};
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static const unsigned int drif0_data1_c_pins[] = {
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/* D1 */
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RCAR_GP_PIN(5, 14),
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};
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static const unsigned int drif0_data1_c_mux[] = {
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RIF0_D1_C_MARK,
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};
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/* - DRIF1 --------------------------------------------------------------- */
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static const unsigned int drif1_ctrl_a_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
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};
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static const unsigned int drif1_ctrl_a_mux[] = {
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RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
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};
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static const unsigned int drif1_data0_a_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 19),
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};
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static const unsigned int drif1_data0_a_mux[] = {
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RIF1_D0_A_MARK,
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};
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static const unsigned int drif1_data1_a_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 20),
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};
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static const unsigned int drif1_data1_a_mux[] = {
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RIF1_D1_A_MARK,
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};
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static const unsigned int drif1_ctrl_b_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
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};
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static const unsigned int drif1_ctrl_b_mux[] = {
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RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
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};
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static const unsigned int drif1_data0_b_pins[] = {
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/* D0 */
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RCAR_GP_PIN(5, 7),
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};
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static const unsigned int drif1_data0_b_mux[] = {
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RIF1_D0_B_MARK,
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};
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static const unsigned int drif1_data1_b_pins[] = {
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/* D1 */
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RCAR_GP_PIN(5, 8),
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};
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static const unsigned int drif1_data1_b_mux[] = {
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RIF1_D1_B_MARK,
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};
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static const unsigned int drif1_ctrl_c_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
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};
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static const unsigned int drif1_ctrl_c_mux[] = {
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RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
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};
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static const unsigned int drif1_data0_c_pins[] = {
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/* D0 */
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RCAR_GP_PIN(5, 6),
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};
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static const unsigned int drif1_data0_c_mux[] = {
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RIF1_D0_C_MARK,
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};
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static const unsigned int drif1_data1_c_pins[] = {
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/* D1 */
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RCAR_GP_PIN(5, 10),
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};
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static const unsigned int drif1_data1_c_mux[] = {
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RIF1_D1_C_MARK,
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};
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/* - DRIF2 --------------------------------------------------------------- */
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static const unsigned int drif2_ctrl_a_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
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};
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static const unsigned int drif2_ctrl_a_mux[] = {
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RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
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};
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static const unsigned int drif2_data0_a_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 7),
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};
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static const unsigned int drif2_data0_a_mux[] = {
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RIF2_D0_A_MARK,
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};
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static const unsigned int drif2_data1_a_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 10),
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};
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static const unsigned int drif2_data1_a_mux[] = {
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RIF2_D1_A_MARK,
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};
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static const unsigned int drif2_ctrl_b_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
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};
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static const unsigned int drif2_ctrl_b_mux[] = {
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RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
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};
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static const unsigned int drif2_data0_b_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 30),
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};
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static const unsigned int drif2_data0_b_mux[] = {
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RIF2_D0_B_MARK,
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};
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static const unsigned int drif2_data1_b_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 31),
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};
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static const unsigned int drif2_data1_b_mux[] = {
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RIF2_D1_B_MARK,
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};
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/* - DRIF3 --------------------------------------------------------------- */
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static const unsigned int drif3_ctrl_a_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
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};
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static const unsigned int drif3_ctrl_a_mux[] = {
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RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
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};
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static const unsigned int drif3_data0_a_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 19),
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};
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static const unsigned int drif3_data0_a_mux[] = {
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RIF3_D0_A_MARK,
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};
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static const unsigned int drif3_data1_a_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 20),
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};
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static const unsigned int drif3_data1_a_mux[] = {
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RIF3_D1_A_MARK,
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};
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static const unsigned int drif3_ctrl_b_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
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};
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static const unsigned int drif3_ctrl_b_mux[] = {
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RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
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};
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static const unsigned int drif3_data0_b_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 28),
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};
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static const unsigned int drif3_data0_b_mux[] = {
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RIF3_D0_B_MARK,
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};
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static const unsigned int drif3_data1_b_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 29),
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};
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static const unsigned int drif3_data1_b_mux[] = {
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RIF3_D1_B_MARK,
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};
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/* - HSCIF0 ----------------------------------------------------------------- */
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static const unsigned int hscif0_data_pins[] = {
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/* RX, TX */
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@ -3348,6 +3563,36 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(canfd0_data_a),
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SH_PFC_PIN_GROUP(canfd0_data_b),
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SH_PFC_PIN_GROUP(canfd1_data),
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SH_PFC_PIN_GROUP(drif0_ctrl_a),
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SH_PFC_PIN_GROUP(drif0_data0_a),
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SH_PFC_PIN_GROUP(drif0_data1_a),
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SH_PFC_PIN_GROUP(drif0_ctrl_b),
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SH_PFC_PIN_GROUP(drif0_data0_b),
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SH_PFC_PIN_GROUP(drif0_data1_b),
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SH_PFC_PIN_GROUP(drif0_ctrl_c),
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SH_PFC_PIN_GROUP(drif0_data0_c),
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SH_PFC_PIN_GROUP(drif0_data1_c),
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SH_PFC_PIN_GROUP(drif1_ctrl_a),
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SH_PFC_PIN_GROUP(drif1_data0_a),
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SH_PFC_PIN_GROUP(drif1_data1_a),
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SH_PFC_PIN_GROUP(drif1_ctrl_b),
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SH_PFC_PIN_GROUP(drif1_data0_b),
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SH_PFC_PIN_GROUP(drif1_data1_b),
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SH_PFC_PIN_GROUP(drif1_ctrl_c),
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SH_PFC_PIN_GROUP(drif1_data0_c),
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SH_PFC_PIN_GROUP(drif1_data1_c),
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SH_PFC_PIN_GROUP(drif2_ctrl_a),
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SH_PFC_PIN_GROUP(drif2_data0_a),
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SH_PFC_PIN_GROUP(drif2_data1_a),
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SH_PFC_PIN_GROUP(drif2_ctrl_b),
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SH_PFC_PIN_GROUP(drif2_data0_b),
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SH_PFC_PIN_GROUP(drif2_data1_b),
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SH_PFC_PIN_GROUP(drif3_ctrl_a),
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SH_PFC_PIN_GROUP(drif3_data0_a),
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SH_PFC_PIN_GROUP(drif3_data1_a),
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SH_PFC_PIN_GROUP(drif3_ctrl_b),
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SH_PFC_PIN_GROUP(drif3_data0_b),
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SH_PFC_PIN_GROUP(drif3_data1_b),
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SH_PFC_PIN_GROUP(hscif0_data),
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SH_PFC_PIN_GROUP(hscif0_clk),
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SH_PFC_PIN_GROUP(hscif0_ctrl),
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@ -3631,6 +3876,48 @@ static const char * const canfd1_groups[] = {
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"canfd1_data",
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};
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static const char * const drif0_groups[] = {
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"drif0_ctrl_a",
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"drif0_data0_a",
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"drif0_data1_a",
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"drif0_ctrl_b",
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"drif0_data0_b",
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"drif0_data1_b",
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"drif0_ctrl_c",
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"drif0_data0_c",
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"drif0_data1_c",
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};
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static const char * const drif1_groups[] = {
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"drif1_ctrl_a",
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"drif1_data0_a",
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"drif1_data1_a",
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"drif1_ctrl_b",
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"drif1_data0_b",
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"drif1_data1_b",
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"drif1_ctrl_c",
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"drif1_data0_c",
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"drif1_data1_c",
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};
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static const char * const drif2_groups[] = {
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"drif2_ctrl_a",
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"drif2_data0_a",
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"drif2_data1_a",
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"drif2_ctrl_b",
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"drif2_data0_b",
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"drif2_data1_b",
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};
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static const char * const drif3_groups[] = {
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"drif3_ctrl_a",
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"drif3_data0_a",
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"drif3_data1_a",
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"drif3_ctrl_b",
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"drif3_data0_b",
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"drif3_data1_b",
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};
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static const char * const hscif0_groups[] = {
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"hscif0_data",
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"hscif0_clk",
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@ -3974,6 +4261,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(can_clk),
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SH_PFC_FUNCTION(canfd0),
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SH_PFC_FUNCTION(canfd1),
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SH_PFC_FUNCTION(drif0),
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SH_PFC_FUNCTION(drif1),
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SH_PFC_FUNCTION(drif2),
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SH_PFC_FUNCTION(drif3),
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SH_PFC_FUNCTION(hscif0),
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SH_PFC_FUNCTION(hscif1),
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SH_PFC_FUNCTION(hscif2),
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