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clk: zynqmp: Update fraction clock check from custom type flags
Older firmware version sets BIT(13) in clkflag to mark a divider as fractional divider. Updated firmware version sets BIT(4) in type flags to mark a divider as fractional divider since BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk framework flags. To support both old and new firmware version, consider BIT(13) from clkflag and BIT(4) from type_flag to check if divider is fractional or not. To maintain compatibility BIT(13) of clkflag in firmware will not be used in future for any purpose and will be marked as unused. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lkml.kernel.org/r/1584048699-24186-3-git-send-email-jolly.shah@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -26,6 +26,7 @@
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container_of(_hw, struct zynqmp_clk_divider, hw)
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#define CLK_FRAC BIT(13) /* has a fractional parent */
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#define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */
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/**
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* struct zynqmp_clk_divider - adjustable divider clock
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@ -320,7 +321,8 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
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init.num_parents = 1;
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/* struct clk_divider assignments */
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div->is_frac = !!(nodes->flag & CLK_FRAC);
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div->is_frac = !!((nodes->flag & CLK_FRAC) |
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(nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
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div->flags = nodes->type_flag;
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div->hw.init = &init;
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div->clk_id = clk_id;
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