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ASoC: cs42l42: Use bclk from hw_params if set_sysclk was not called
Add support for reading the source clock from snd_soc_params_to_bclk so the machine driver is not required to call cs42l42_set_sysclk Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210306185553.62053-13-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
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c5b8ee0879
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@ -588,10 +588,16 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
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{
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struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
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int i;
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u32 clk;
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u32 fsync;
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if (!cs42l42->sclk)
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clk = cs42l42->bclk;
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else
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clk = cs42l42->sclk;
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for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
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if (pll_ratio_table[i].sclk == cs42l42->sclk) {
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if (pll_ratio_table[i].sclk == clk) {
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/* Configure the internal sample rate */
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snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
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CS42L42_INTERNAL_FS_MASK,
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@ -611,12 +617,12 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
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(pll_ratio_table[i].mclk_div <<
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CS42L42_MCLKDIV_SHIFT));
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/* Set up the LRCLK */
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fsync = cs42l42->sclk / cs42l42->srate;
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if (((fsync * cs42l42->srate) != cs42l42->sclk)
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fsync = clk / cs42l42->srate;
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if (((fsync * cs42l42->srate) != clk)
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|| ((fsync % 2) != 0)) {
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dev_err(component->dev,
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"Unsupported sclk %d/sample rate %d\n",
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cs42l42->sclk,
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clk,
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cs42l42->srate);
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return -EINVAL;
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}
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@ -788,6 +794,7 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
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unsigned int val = 0;
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cs42l42->srate = params_rate(params);
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cs42l42->bclk = snd_soc_params_to_bclk(params);
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switch(substream->stream) {
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case SNDRV_PCM_STREAM_CAPTURE:
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@ -921,6 +928,8 @@ static struct snd_soc_dai_driver cs42l42_dai = {
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = CS42L42_FORMATS,
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},
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.symmetric_rate = 1,
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.symmetric_sample_bits = 1,
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.ops = &cs42l42_ops,
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};
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@ -771,6 +771,7 @@ struct cs42l42_private {
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struct gpio_desc *reset_gpio;
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struct completion pdn_done;
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struct snd_soc_jack jack;
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int bclk;
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u32 sclk;
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u32 srate;
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u8 plug_state;
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