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x86/mce: Clarify comments regarding deferred error
Deferred errors indicate errors that hardware could not fix. But it still does not cause any interruption to program flow. So it does not generate any #MC and UC bit in MCx_STATUS is not set. Correct comment. Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1457021458-2522-5-git-send-email-Aravind.Gopalakrishnan@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -40,7 +40,7 @@
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#define MCI_STATUS_AR (1ULL<<55) /* Action required */
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/* AMD-specific bits */
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#define MCI_STATUS_DEFERRED (1ULL<<44) /* declare an uncorrected error */
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#define MCI_STATUS_DEFERRED (1ULL<<44) /* uncorrected error, deferred exception */
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#define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */
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#define MCI_STATUS_TCC (1ULL<<55) /* Task context corrupt */
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