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arm: dts: mt7623: add display subsystem related device nodes
Add display subsystem related device nodes for MT7623. Signed-off-by: chunhui dai <chunhui.dai@mediatek.com> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Tested-by: Frank Wunderlich <frank-w@public-files.de> Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://lore.kernel.org/r/20200904110002.88966-4-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Ryder Lee
Matthias Brugger
parent
c0d66c560e
commit
2c78f4bd2b
@ -21,6 +21,19 @@
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stdout-path = "serial2:115200n8";
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};
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connector {
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compatible = "hdmi-connector";
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label = "hdmi";
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type = "d";
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ddc-i2c-bus = <&hdmiddc0>;
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi0_out>;
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};
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};
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};
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cpus {
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cpu@0 {
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proc-supply = <&mt6323_vproc_reg>;
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@ -114,10 +127,18 @@
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};
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};
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&bls {
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status = "okay";
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};
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&btif {
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status = "okay";
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};
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&cec {
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status = "okay";
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};
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&cir {
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pinctrl-names = "default";
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pinctrl-0 = <&cir_pins_a>;
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@ -128,6 +149,21 @@
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status = "okay";
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};
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&dpi0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpi0_out: endpoint {
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remote-endpoint = <&hdmi0_in>;
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};
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};
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};
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};
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ð {
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status = "okay";
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@ -199,6 +235,42 @@
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};
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};
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&hdmi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_pins_a>;
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi0_in: endpoint {
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remote-endpoint = <&dpi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi0_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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&hdmiddc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_ddc_pins_a>;
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status = "okay";
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};
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&hdmi_phy {
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mediatek,ibias = <0xa>;
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mediatek,ibias_up = <0x1c>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins_a>;
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@ -24,6 +24,19 @@
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stdout-path = "serial2:115200n8";
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};
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connector {
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compatible = "hdmi-connector";
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label = "hdmi";
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type = "d";
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ddc-i2c-bus = <&hdmiddc0>;
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi0_out>;
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};
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};
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};
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cpus {
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cpu@0 {
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proc-supply = <&mt6323_vproc_reg>;
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@ -106,10 +119,18 @@
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};
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};
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&bls {
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status = "okay";
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};
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&btif {
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status = "okay";
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};
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&cec {
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status = "okay";
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};
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&cir {
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pinctrl-names = "default";
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pinctrl-0 = <&cir_pins_a>;
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@ -120,6 +141,21 @@
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status = "okay";
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};
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&dpi0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpi0_out: endpoint {
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remote-endpoint = <&hdmi0_in>;
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};
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};
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};
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};
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ð {
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status = "okay";
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@ -203,6 +239,42 @@
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};
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};
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&hdmi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_pins_a>;
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi0_in: endpoint {
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remote-endpoint = <&dpi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi0_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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&hdmiddc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_ddc_pins_a>;
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status = "okay";
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};
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&hdmi_phy {
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mediatek,ibias = <0xa>;
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mediatek,ibias_up = <0x1c>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins_a>;
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@ -10,6 +10,11 @@
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#include <dt-bindings/memory/mt2701-larb-port.h>
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/ {
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aliases {
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rdma0 = &rdma0;
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rdma1 = &rdma1;
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};
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g3dsys: syscon@13000000 {
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compatible = "mediatek,mt7623-g3dsys",
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"mediatek,mt2701-g3dsys",
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@ -131,4 +136,171 @@
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clock-names = "apb", "smi", "async";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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ovl: ovl@14007000 {
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compatible = "mediatek,mt7623-disp-ovl",
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"mediatek,mt2701-disp-ovl";
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reg = <0 0x14007000 0 0x1000>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DISP_OVL>;
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iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
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mediatek,larb = <&larb0>;
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};
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rdma0: rdma@14008000 {
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compatible = "mediatek,mt7623-disp-rdma",
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"mediatek,mt2701-disp-rdma";
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reg = <0 0x14008000 0 0x1000>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DISP_RDMA>;
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iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
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mediatek,larb = <&larb0>;
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};
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wdma@14009000 {
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compatible = "mediatek,mt7623-disp-wdma",
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"mediatek,mt2701-disp-wdma";
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reg = <0 0x14009000 0 0x1000>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DISP_WDMA>;
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iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
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mediatek,larb = <&larb0>;
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};
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bls: pwm@1400a000 {
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compatible = "mediatek,mt7623-disp-pwm",
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"mediatek,mt2701-disp-pwm";
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reg = <0 0x1400a000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
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<&mmsys CLK_MM_DISP_BLS>;
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clock-names = "main", "mm";
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status = "disabled";
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};
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color: color@1400b000 {
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compatible = "mediatek,mt7623-disp-color",
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"mediatek,mt2701-disp-color";
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reg = <0 0x1400b000 0 0x1000>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DISP_COLOR>;
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};
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dsi: dsi@1400c000 {
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compatible = "mediatek,mt7623-dsi",
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"mediatek,mt2701-dsi";
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reg = <0 0x1400c000 0 0x1000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DSI_ENGINE>,
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<&mmsys CLK_MM_DSI_DIG>,
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<&mipi_tx0>;
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clock-names = "engine", "digital", "hs";
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phys = <&mipi_tx0>;
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phy-names = "dphy";
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status = "disabled";
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};
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mutex: mutex@1400e000 {
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compatible = "mediatek,mt7623-disp-mutex",
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"mediatek,mt2701-disp-mutex";
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reg = <0 0x1400e000 0 0x1000>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_MUTEX_32K>;
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};
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rdma1: rdma@14012000 {
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compatible = "mediatek,mt7623-disp-rdma",
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"mediatek,mt2701-disp-rdma";
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reg = <0 0x14012000 0 0x1000>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DISP_RDMA1>;
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iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
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mediatek,larb = <&larb0>;
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};
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dpi0: dpi@14014000 {
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compatible = "mediatek,mt7623-dpi",
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"mediatek,mt2701-dpi";
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reg = <0 0x14014000 0 0x1000>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DPI1_DIGL>,
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<&mmsys CLK_MM_DPI1_ENGINE>,
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<&apmixedsys CLK_APMIXED_TVDPLL>;
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clock-names = "pixel", "engine", "pll";
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status = "disabled";
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};
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hdmi0: hdmi@14015000 {
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compatible = "mediatek,mt7623-hdmi",
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"mediatek,mt2701-hdmi";
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reg = <0 0x14015000 0 0x400>;
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clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
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<&mmsys CLK_MM_HDMI_PLL>,
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<&mmsys CLK_MM_HDMI_AUDIO>,
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<&mmsys CLK_MM_HDMI_SPDIF>;
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clock-names = "pixel", "pll", "bclk", "spdif";
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phys = <&hdmi_phy>;
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phy-names = "hdmi";
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mediatek,syscon-hdmi = <&mmsys 0x900>;
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cec = <&cec>;
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status = "disabled";
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};
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mipi_tx0: mipi-dphy@10010000 {
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compatible = "mediatek,mt7623-mipi-tx",
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"mediatek,mt2701-mipi-tx";
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reg = <0 0x10010000 0 0x90>;
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clocks = <&clk26m>;
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clock-output-names = "mipi_tx0_pll";
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#clock-cells = <0>;
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#phy-cells = <0>;
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};
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cec: cec@10012000 {
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compatible = "mediatek,mt7623-cec",
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"mediatek,mt8173-cec";
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reg = <0 0x10012000 0 0xbc>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_CEC>;
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status = "disabled";
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};
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hdmi_phy: phy@10209100 {
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compatible = "mediatek,mt7623-hdmi-phy",
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"mediatek,mt2701-hdmi-phy";
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reg = <0 0x10209100 0 0x24>;
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clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
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clock-names = "pll_ref";
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clock-output-names = "hdmitx_dig_cts";
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#clock-cells = <0>;
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#phy-cells = <0>;
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status = "disabled";
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};
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hdmiddc0: i2c@11013000 {
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compatible = "mediatek,mt7623-hdmi-ddc",
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"mediatek,mt8173-hdmi-ddc";
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
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reg = <0 0x11013000 0 0x1C>;
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clocks = <&pericfg CLK_PERI_I2C3>;
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clock-names = "ddc-i2c";
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status = "disabled";
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};
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};
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&pio {
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hdmi_pins_a: hdmi-default {
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pins-hdmi {
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pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>;
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input-enable;
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bias-pull-down;
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};
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};
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hdmi_ddc_pins_a: hdmi_ddc-default {
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pins-hdmi-ddc {
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pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>,
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<MT7623_PIN_125_GPIO125_FUNC_HDMISD>;
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};
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};
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};
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