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ASoC: davinci-mcasp: Configure xxTDM, xxFMT and xxFMCT registers synchronously

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These registers can be configured synchronously for playback and capture.
Furthermore when McASP is in master and sync mode the capture operation
needs the TX path to be configured in order to be able to provide the needed
clocks for the bus.
xxFMT and xxFMCT registers has been already configured for both TX and RX
other places in the driver.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Peter Ujfalusi 2014-01-30 15:15:23 +02:00 committed by Mark Brown
parent 662ffae9ed
commit 2c56c4c27c
1 changed files with 25 additions and 27 deletions
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52
sound/soc/davinci/davinci-mcasp.c
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@ -524,12 +524,18 @@ static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
return 0;
}
static void mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
{
int i, active_slots;
u32 mask = 0;
u32 busel = 0;
if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
dev_err(mcasp->dev, "tdm slot %d not supported\n",
mcasp->tdm_slots);
return -EINVAL;
}
active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
for (i = 0; i < active_slots; i++)
mask |= (1 << i);
@ -539,35 +545,21 @@ static void mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
if (!mcasp->dat_port)
busel = TXSEL;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* bit stream is MSB first with no delay */
/* DSP_B mode */
mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
else
printk(KERN_ERR "playback tdm slot %d not supported\n",
mcasp->tdm_slots);
} else {
/* bit stream is MSB first with no delay */
/* DSP_B mode */
mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
else
printk(KERN_ERR "capture tdm slot %d not supported\n",
mcasp->tdm_slots);
}
return 0;
}
/* S/PDIF */
static void mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
{
/* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
and LSB first */
@ -589,6 +581,8 @@ static void mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
/* Enable the DIT */
mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
return 0;
}
static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
@ -605,6 +599,7 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
u8 slots = mcasp->tdm_slots;
u8 active_serializers;
int channels;
int ret;
struct snd_interval *pcm_channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
channels = pcm_channels->min;
@ -619,9 +614,12 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
fifo_level = mcasp->rxnumevt * active_serializers;
if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
mcasp_dit_hw_param(mcasp);
ret = mcasp_dit_hw_param(mcasp);
else
mcasp_i2s_hw_param(mcasp, substream->stream);
ret = mcasp_i2s_hw_param(mcasp, substream->stream);
if (ret)
return ret;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_U8: