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KVM/arm64 fixes for v5.10, take #3
- Allow userspace to downgrade ID_AA64PFR0_EL1.CSV2 - Inject UNDEF on SCXTNUM_ELx access -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAl+tsAQPHG1hekBrZXJu ZWwub3JnAAoJECPQ0LrRPXpDieIP/06lrDbhKUv1BX5oOlNFKifsaxmrCiP2A9Ql 1RiT1wI4Ba+QcgtnyUOI/SQgNx4Z+LkUFghkqP3TvtPEj3Y3zhCFiyz3wn/H0YJA eZ5kI5XkG+9NOdzpyhNKiN2ZOVz0/RpHnIyHWU1SFD3Ky58xHsI1w5boNcTYJDXE IVVAQ05HzNMOnqEnfS3Z2Oe99jiYXS1C80Rf2WvQuQQW6Nwu3J0W5VZztw/E9VG0 wbivuOaFzk2Zee30oTXxkJfFDS7m3fZ2dXvHSUB9Luv3GMAFp/sK2ZmEg7ZUiAl1 zBPW35jHv1bahU88IQ7LhvTa+Tg6aEGnCrjHO9JiCx4z0VLnEz86AzejItaGvRu7 SGf7taj4xRfUVxlJsW1i5Nel7hpmk8ip59hWUq5jTu7bPQvnEFpSfWANgobQrGF4 pAtYUyaJcU5hRml4NUOy/gGkBzZSDloe1ClDUsdVZrbMKSjnATD8/0Z2oxHthVI1 vvzovTXOQ7LK81Qm9GZ6Xlj0vXJh2V91wMTxy82lK5PAmKuVWvgqOWbH7e8YX+2T VlY5jkIyjwj9vwyMQHmaR5f01eZotYVTM+YKZcjx6O+1MGkrSxZkVptf0g8Bj0X3 VmCYHyA5LIil8bx58kLfoZhAtjOaAFf+j5XCTjP0zCB4mVHcrCk0rLBPyvPsZB73 I3WFpQPq =eZCZ -----END PGP SIGNATURE----- Merge tag 'kvmarm-fixes-5.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 fixes for v5.10, take #3 - Allow userspace to downgrade ID_AA64PFR0_EL1.CSV2 - Inject UNDEF on SCXTNUM_ELx access
This commit is contained in:
Paolo Bonzini
commit
2c38234c42
@ -118,6 +118,8 @@ struct kvm_arch {
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*/
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unsigned long *pmu_filter;
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unsigned int pmuver;
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u8 pfr0_csv2;
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};
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struct kvm_vcpu_fault_info {
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@ -372,6 +372,8 @@
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#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
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#define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
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#define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7)
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#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
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#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
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@ -404,6 +406,8 @@
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#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
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#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
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#define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
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/* Definitions for system register interface to AMU for ARMv8.4 onwards */
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#define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
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#define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
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@ -102,6 +102,20 @@ static int kvm_arm_default_max_vcpus(void)
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return vgic_present ? kvm_vgic_get_max_vcpus() : KVM_MAX_VCPUS;
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}
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static void set_default_csv2(struct kvm *kvm)
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{
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/*
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* The default is to expose CSV2 == 1 if the HW isn't affected.
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* Although this is a per-CPU feature, we make it global because
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* asymmetric systems are just a nuisance.
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*
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* Userspace can override this as long as it doesn't promise
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* the impossible.
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*/
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if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED)
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kvm->arch.pfr0_csv2 = 1;
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}
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/**
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* kvm_arch_init_vm - initializes a VM data structure
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* @kvm: pointer to the KVM struct
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@ -127,6 +141,8 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
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/* The maximum number of VCPUs is limited by the host's GIC model */
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kvm->arch.max_vcpus = kvm_arm_default_max_vcpus();
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set_default_csv2(kvm);
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return ret;
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out_free_stage2_pgd:
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kvm_free_stage2_pgd(&kvm->arch.mmu);
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@ -1038,7 +1038,7 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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{ SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
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access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
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static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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kvm_inject_undefined(vcpu);
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@ -1047,24 +1047,10 @@ static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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}
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/* Macro to expand the AMU counter and type registers*/
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#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu }
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#define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), access_amu }
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#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu }
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#define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), access_amu }
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static bool trap_ptrauth(struct kvm_vcpu *vcpu,
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struct sys_reg_params *p,
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const struct sys_reg_desc *rd)
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{
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/*
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* If we land here, that is because we didn't fixup the access on exit
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* by allowing the PtrAuth sysregs. The only way this happens is when
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* the guest does not have PtrAuth support enabled.
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*/
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kvm_inject_undefined(vcpu);
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return false;
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}
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#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
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#define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
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#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
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#define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
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static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd)
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@ -1072,8 +1058,14 @@ static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
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return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
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}
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/*
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* If we land here on a PtrAuth access, that is because we didn't
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* fixup the access on exit by allowing the PtrAuth sysregs. The only
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* way this happens is when the guest does not have PtrAuth support
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* enabled.
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*/
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#define __PTRAUTH_KEY(k) \
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{ SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \
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{ SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
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.visibility = ptrauth_visibility}
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#define PTRAUTH_KEY(k) \
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@ -1128,9 +1120,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
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if (!vcpu_has_sve(vcpu))
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val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
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val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
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if (!(val & (0xfUL << ID_AA64PFR0_CSV2_SHIFT)) &&
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arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED)
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val |= (1UL << ID_AA64PFR0_CSV2_SHIFT);
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val &= ~(0xfUL << ID_AA64PFR0_CSV2_SHIFT);
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val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT);
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} else if (id == SYS_ID_AA64PFR1_EL1) {
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val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
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} else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
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@ -1213,6 +1204,40 @@ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
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return REG_HIDDEN;
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}
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static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd,
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const struct kvm_one_reg *reg, void __user *uaddr)
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{
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const u64 id = sys_reg_to_index(rd);
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int err;
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u64 val;
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u8 csv2;
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err = reg_from_user(&val, uaddr, id);
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if (err)
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return err;
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/*
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* Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
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* it doesn't promise more than what is actually provided (the
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* guest could otherwise be covered in ectoplasmic residue).
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*/
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csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT);
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if (csv2 > 1 ||
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(csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
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return -EINVAL;
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/* We can only differ with CSV2, and anything else is an error */
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val ^= read_id_reg(vcpu, rd, false);
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val &= ~(0xFUL << ID_AA64PFR0_CSV2_SHIFT);
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if (val)
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return -EINVAL;
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vcpu->kvm->arch.pfr0_csv2 = csv2;
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return 0;
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}
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/*
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* cpufeature ID register user accessors
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*
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@ -1341,13 +1366,6 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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return true;
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}
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static bool access_mte_regs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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kvm_inject_undefined(vcpu);
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return false;
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}
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/* sys_reg_desc initialiser for known cpufeature ID registers */
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#define ID_SANITISED(name) { \
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SYS_DESC(SYS_##name), \
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@ -1472,7 +1490,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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/* AArch64 ID registers */
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/* CRm=4 */
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ID_SANITISED(ID_AA64PFR0_EL1),
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{ SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
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.get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
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ID_SANITISED(ID_AA64PFR1_EL1),
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ID_UNALLOCATED(4,2),
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ID_UNALLOCATED(4,3),
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@ -1515,8 +1534,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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{ SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
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{ SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
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{ SYS_DESC(SYS_RGSR_EL1), access_mte_regs },
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{ SYS_DESC(SYS_GCR_EL1), access_mte_regs },
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{ SYS_DESC(SYS_RGSR_EL1), undef_access },
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{ SYS_DESC(SYS_GCR_EL1), undef_access },
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{ SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
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{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
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@ -1542,8 +1561,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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{ SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
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{ SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
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{ SYS_DESC(SYS_TFSR_EL1), access_mte_regs },
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{ SYS_DESC(SYS_TFSRE0_EL1), access_mte_regs },
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{ SYS_DESC(SYS_TFSR_EL1), undef_access },
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{ SYS_DESC(SYS_TFSRE0_EL1), undef_access },
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{ SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
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{ SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
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@ -1579,6 +1598,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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{ SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
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{ SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
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{ SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
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{ SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
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{ SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
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@ -1607,14 +1628,16 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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{ SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
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{ SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
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{ SYS_DESC(SYS_AMCR_EL0), access_amu },
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{ SYS_DESC(SYS_AMCFGR_EL0), access_amu },
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{ SYS_DESC(SYS_AMCGCR_EL0), access_amu },
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{ SYS_DESC(SYS_AMUSERENR_EL0), access_amu },
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{ SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu },
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{ SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu },
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{ SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu },
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{ SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu },
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{ SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
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{ SYS_DESC(SYS_AMCR_EL0), undef_access },
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{ SYS_DESC(SYS_AMCFGR_EL0), undef_access },
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{ SYS_DESC(SYS_AMCGCR_EL0), undef_access },
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{ SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
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{ SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
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{ SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
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{ SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
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{ SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
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AMU_AMEVCNTR0_EL0(0),
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AMU_AMEVCNTR0_EL0(1),
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AMU_AMEVCNTR0_EL0(2),
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