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clk: sunxi-ng: mux: Add support for mux tables
Some clock muxes have holes, i.e. invalid or unconnected inputs, between parent mux values. Add support for specifying a mux table to map clock parents to mux values. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -107,6 +107,15 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common,
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parent = reg >> cm->shift;
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parent = reg >> cm->shift;
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parent &= (1 << cm->width) - 1;
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parent &= (1 << cm->width) - 1;
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if (cm->table) {
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int num_parents = clk_hw_get_num_parents(&common->hw);
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int i;
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for (i = 0; i < num_parents; i++)
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if (cm->table[i] == parent)
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return i;
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}
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return parent;
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return parent;
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}
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}
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@ -117,6 +126,9 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
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unsigned long flags;
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unsigned long flags;
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u32 reg;
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u32 reg;
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if (cm->table)
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index = cm->table[index];
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spin_lock_irqsave(common->lock, flags);
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spin_lock_irqsave(common->lock, flags);
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reg = readl(common->base + common->reg);
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reg = readl(common->base + common->reg);
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@ -6,8 +6,9 @@
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#include "ccu_common.h"
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#include "ccu_common.h"
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struct ccu_mux_internal {
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struct ccu_mux_internal {
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u8 shift;
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u8 shift;
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u8 width;
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u8 width;
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const u8 *table;
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struct {
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struct {
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u8 index;
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u8 index;
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@ -21,12 +22,16 @@ struct ccu_mux_internal {
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} variable_prediv;
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} variable_prediv;
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};
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};
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#define _SUNXI_CCU_MUX(_shift, _width) \
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#define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \
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{ \
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{ \
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.shift = _shift, \
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.shift = _shift, \
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.width = _width, \
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.width = _width, \
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.table = _table, \
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}
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}
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#define _SUNXI_CCU_MUX(_shift, _width) \
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_SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
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struct ccu_mux {
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struct ccu_mux {
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u16 reg;
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u16 reg;
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u32 enable;
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u32 enable;
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