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drm/nv50: use "nv86" tlb flush method on everything except 0x50/0xac
It has been reported that this greatly improves (and possibly fixes completely) the stability of NVA3+ chipsets. In traces of my NVA8, NVIDIA now appear to be doing this too. The most recent traces of 0x50 and 0xac I could find don't show NVIDIA checking PGRAPH status on these flushes, so for now, we won't either. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -1190,7 +1190,7 @@ extern int nv50_graph_load_context(struct nouveau_channel *);
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extern int nv50_graph_unload_context(struct drm_device *);
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extern int nv50_grctx_init(struct nouveau_grctx *);
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extern void nv50_graph_tlb_flush(struct drm_device *dev);
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extern void nv86_graph_tlb_flush(struct drm_device *dev);
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extern void nv84_graph_tlb_flush(struct drm_device *dev);
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extern struct nouveau_enum nv50_data_error_names[];
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/* nvc0_graph.c */
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@ -376,15 +376,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->graph.destroy_context = nv50_graph_destroy_context;
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engine->graph.load_context = nv50_graph_load_context;
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engine->graph.unload_context = nv50_graph_unload_context;
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if (dev_priv->chipset != 0x86)
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if (dev_priv->chipset == 0x50 ||
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dev_priv->chipset == 0xac)
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engine->graph.tlb_flush = nv50_graph_tlb_flush;
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else {
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/* from what i can see nvidia do this on every
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* pre-NVA3 board except NVAC, but, we've only
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* ever seen problems on NV86
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*/
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engine->graph.tlb_flush = nv86_graph_tlb_flush;
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}
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else
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engine->graph.tlb_flush = nv84_graph_tlb_flush;
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engine->fifo.channels = 128;
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engine->fifo.init = nv50_fifo_init;
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engine->fifo.takedown = nv50_fifo_takedown;
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@ -503,7 +503,7 @@ nv50_graph_tlb_flush(struct drm_device *dev)
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}
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void
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nv86_graph_tlb_flush(struct drm_device *dev)
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nv84_graph_tlb_flush(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
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