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KVM: MMU: Map device MMIO as UC in EPT
Software are not allow to access device MMIO using cacheable memory type, the patch limit MMIO region with UC and WC(guest can select WC using PAT and PCD/PWT). Signed-off-by: Sheng Yang <sheng@linux.intel.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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@ -1698,8 +1698,13 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
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if (largepage)
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if (largepage)
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spte |= PT_PAGE_SIZE_MASK;
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spte |= PT_PAGE_SIZE_MASK;
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if (mt_mask) {
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if (mt_mask) {
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mt_mask = get_memory_type(vcpu, gfn) <<
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if (!kvm_is_mmio_pfn(pfn)) {
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kvm_x86_ops->get_mt_mask_shift();
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mt_mask = get_memory_type(vcpu, gfn) <<
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kvm_x86_ops->get_mt_mask_shift();
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mt_mask |= VMX_EPT_IGMT_BIT;
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} else
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mt_mask = MTRR_TYPE_UNCACHABLE <<
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kvm_x86_ops->get_mt_mask_shift();
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spte |= mt_mask;
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spte |= mt_mask;
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}
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}
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@ -3687,8 +3687,7 @@ static int __init vmx_init(void)
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if (vm_need_ept()) {
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if (vm_need_ept()) {
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bypass_guest_pf = 0;
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bypass_guest_pf = 0;
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kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
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kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
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VMX_EPT_WRITABLE_MASK |
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VMX_EPT_WRITABLE_MASK);
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VMX_EPT_IGMT_BIT);
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kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
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kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
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VMX_EPT_EXECUTABLE_MASK,
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VMX_EPT_EXECUTABLE_MASK,
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VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
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VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
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