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MIPS: Hibernate: flush TLB entries earlier
We found that TLB mismatch not only happens after kernel resume, but also happens during snapshot restore. So move it to the beginning of swsusp_arch_suspend(). Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: <stable@vger.kernel.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9621/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -30,6 +30,8 @@ LEAF(swsusp_arch_suspend)
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END(swsusp_arch_suspend)
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END(swsusp_arch_suspend)
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LEAF(swsusp_arch_resume)
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LEAF(swsusp_arch_resume)
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/* Avoid TLB mismatch during and after kernel resume */
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jal local_flush_tlb_all
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PTR_L t0, restore_pblist
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PTR_L t0, restore_pblist
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0:
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0:
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PTR_L t1, PBE_ADDRESS(t0) /* source */
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PTR_L t1, PBE_ADDRESS(t0) /* source */
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@ -43,7 +45,6 @@ LEAF(swsusp_arch_resume)
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bne t1, t3, 1b
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bne t1, t3, 1b
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PTR_L t0, PBE_NEXT(t0)
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PTR_L t0, PBE_NEXT(t0)
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bnez t0, 0b
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bnez t0, 0b
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jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */
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PTR_LA t0, saved_regs
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PTR_LA t0, saved_regs
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PTR_L ra, PT_R31(t0)
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PTR_L ra, PT_R31(t0)
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PTR_L sp, PT_R29(t0)
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PTR_L sp, PT_R29(t0)
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