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powerpc/mm: Fix tlbie to add AVAL fields for 64K pages

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The if condition check was based on a draft ISA doc. Remove the same.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Aneesh Kumar K.V 2014-04-21 10:37:36 +05:30 committed by Benjamin Herrenschmidt
parent 2d6b63bbdd
commit 29ef7a3e26
1 changed files with 16 additions and 22 deletions
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38
arch/powerpc/mm/hash_native_64.c
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@ -82,17 +82,14 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
va |= penc << 12; va |= penc << 12;
va |= ssize << 8; va |= ssize << 8;
/* Add AVAL part */ /*
if (psize != apsize) { * AVAL bits:
/* * We don't need all the bits, but rest of the bits
* MPSS, 64K base page size and 16MB parge page size * must be ignored by the processor.
* We don't need all the bits, but rest of the bits * vpn cover upto 65 bits of va. (0...65) and we need
* must be ignored by the processor. * 58..64 bits of va.
* vpn cover upto 65 bits of va. (0...65) and we need */
* 58..64 bits of va. va |= (vpn & 0xfe); /* AVAL */
*/
va |= (vpn & 0xfe);
}
va |= 1; /* L */ va |= 1; /* L */
asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2) asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
@ -133,17 +130,14 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
va |= penc << 12; va |= penc << 12;
va |= ssize << 8; va |= ssize << 8;
/* Add AVAL part */ /*
if (psize != apsize) { * AVAL bits:
/* * We don't need all the bits, but rest of the bits
* MPSS, 64K base page size and 16MB parge page size * must be ignored by the processor.
* We don't need all the bits, but rest of the bits * vpn cover upto 65 bits of va. (0...65) and we need
* must be ignored by the processor. * 58..64 bits of va.
* vpn cover upto 65 bits of va. (0...65) and we need */
* 58..64 bits of va. va |= (vpn & 0xfe);
*/
va |= (vpn & 0xfe);
}
va |= 1; /* L */ va |= 1; /* L */
asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
: : "r"(va) : "memory"); : : "r"(va) : "memory");