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powerpc/perf: Expose instruction and data address registers as part of extended regs

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Patch adds support to include Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended
registers. Update the definition of PERF_REG_PMU_MASK_300/31 and
PERF_REG_EXTENDED_MAX to include these SPR's.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Daniel Axtens <dja@axtens.net>
Reviewed-by: Kajol Jain<kjain@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211007065505.27809-4-atrajeev@linux.vnet.ibm.com
This commit is contained in:
Athira Rajeev 2021-10-07 12:25:04 +05:30 committed by Michael Ellerman
parent 02b182e674
commit 29908bbf7b
2 changed files with 11 additions and 4 deletions
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11
arch/powerpc/include/uapi/asm/perf_regs.h
View File

@ -61,17 +61,19 @@ enum perf_event_powerpc_regs {
PERF_REG_POWERPC_PMC4,
PERF_REG_POWERPC_PMC5,
PERF_REG_POWERPC_PMC6,
PERF_REG_POWERPC_SDAR,
PERF_REG_POWERPC_SIAR,
/* Max mask value for interrupt regs w/o extended regs */
PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
/* Max mask value for interrupt regs including extended regs */
PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_PMC6 + 1,
PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_SIAR + 1,
};
#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
/*
* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300
* includes 9 SPRS from MMCR0 to PMC6 excluding the
* includes 11 SPRS from MMCR0 to SIAR excluding the
* unsupported SPRS MMCR3, SIER2 and SIER3.
*/
#define PERF_REG_PMU_MASK_300 \
@ -79,11 +81,12 @@ enum perf_event_powerpc_regs {
(1ULL << PERF_REG_POWERPC_MMCR2) | (1ULL << PERF_REG_POWERPC_PMC1) | \
(1ULL << PERF_REG_POWERPC_PMC2) | (1ULL << PERF_REG_POWERPC_PMC3) | \
(1ULL << PERF_REG_POWERPC_PMC4) | (1ULL << PERF_REG_POWERPC_PMC5) | \
(1ULL << PERF_REG_POWERPC_PMC6))
(1ULL << PERF_REG_POWERPC_PMC6) | (1ULL << PERF_REG_POWERPC_SDAR) | \
(1ULL << PERF_REG_POWERPC_SIAR))
/*
* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31
* includes 12 SPRs from MMCR0 to PMC6.
* includes 14 SPRs from MMCR0 to SIAR.
*/
#define PERF_REG_PMU_MASK_31 \
(PERF_REG_PMU_MASK_300 | (1ULL << PERF_REG_POWERPC_MMCR3) | \

4
arch/powerpc/perf/perf_regs.c
View File

@ -90,7 +90,11 @@ static u64 get_ext_regs_value(int idx)
return mfspr(SPRN_SIER2);
case PERF_REG_POWERPC_SIER3:
return mfspr(SPRN_SIER3);
case PERF_REG_POWERPC_SDAR:
return mfspr(SPRN_SDAR);
#endif
case PERF_REG_POWERPC_SIAR:
return mfspr(SPRN_SIAR);
default: return 0;
}
}