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MIPS: drivers: remove __dev* attributes.

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CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
markings need to be removed.

This change removes the use of __devinit, __devexit_p, __devinitdata,
and __devexit from these drivers.

Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.

Cc: Bill Pemberton <wfp5p@virginia.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman 2012-12-21 14:04:39 -08:00
parent cad5cef62a
commit 28eb0e4661
23 changed files with 61 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/mips/cavium-octeon/serial.c
View File

@ -43,7 +43,7 @@ void octeon_serial_out(struct uart_port *up, int offset, int value)
cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
}
static int __devinit octeon_serial_probe(struct platform_device *pdev)
static int octeon_serial_probe(struct platform_device *pdev)
{
int irq, res;
struct resource *res_mem;

4
arch/mips/include/asm/pci.h
View File

@ -145,7 +145,7 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
extern char * (*pcibios_plat_setup)(char *str);
/* this function parses memory ranges from a device node */
extern void __devinit pci_load_of_ranges(struct pci_controller *hose,
struct device_node *node);
extern void pci_load_of_ranges(struct pci_controller *hose,
struct device_node *node);
#endif /* _ASM_PCI_H */

2
arch/mips/kernel/smp.c
View File

@ -188,7 +188,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
}
/* preload SMP state for boot cpu */
void __devinit smp_prepare_boot_cpu(void)
void smp_prepare_boot_cpu(void)
{
set_cpu_possible(0, true);
set_cpu_online(0, true);

2
arch/mips/lantiq/xway/dma.c
View File

@ -210,7 +210,7 @@ ltq_dma_init_port(int p)
}
EXPORT_SYMBOL_GPL(ltq_dma_init_port);
static int __devinit
static int
ltq_dma_init(struct platform_device *pdev)
{
struct clk *clk;

2
arch/mips/lantiq/xway/gptu.c
View File

@ -133,7 +133,7 @@ static inline void clkdev_add_gptu(struct device *dev, const char *con,
clkdev_add(&clk->cl);
}
static int __devinit gptu_probe(struct platform_device *pdev)
static int gptu_probe(struct platform_device *pdev)
{
struct clk *clk;
struct resource *res;

2
arch/mips/lantiq/xway/xrx200_phy_fw.c
View File

@ -54,7 +54,7 @@ static dma_addr_t xway_gphy_load(struct platform_device *pdev)
return dev_addr;
}
static int __devinit xway_phy_fw_probe(struct platform_device *pdev)
static int xway_phy_fw_probe(struct platform_device *pdev)
{
dma_addr_t fw_addr;
struct property *pp;

6
arch/mips/mti-sead3/sead3-i2c-drv.c
View File

@ -297,7 +297,7 @@ static void sead3_i2c_platform_setup(struct pic32_i2c_platform_data *priv)
priv->base + PIC32_I2CxSTATCLR);
}
static int __devinit sead3_i2c_platform_probe(struct platform_device *pdev)
static int sead3_i2c_platform_probe(struct platform_device *pdev)
{
struct pic32_i2c_platform_data *priv;
struct resource *r;
@ -345,7 +345,7 @@ out:
return ret;
}
static int __devexit sead3_i2c_platform_remove(struct platform_device *pdev)
static int sead3_i2c_platform_remove(struct platform_device *pdev)
{
struct pic32_i2c_platform_data *priv = platform_get_drvdata(pdev);
@ -383,7 +383,7 @@ static struct platform_driver sead3_i2c_platform_driver = {
.owner = THIS_MODULE,
},
.probe = sead3_i2c_platform_probe,
.remove = __devexit_p(sead3_i2c_platform_remove),
.remove = sead3_i2c_platform_remove,
.suspend = sead3_i2c_platform_suspend,
.resume = sead3_i2c_platform_resume,
};

8
arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
View File

@ -304,8 +304,7 @@ static void i2c_platform_disable(struct i2c_platform_data *priv)
pr_debug("i2c_platform_disable\n");
}
static int __devinit
i2c_platform_probe(struct platform_device *pdev)
static int i2c_platform_probe(struct platform_device *pdev)
{
struct i2c_platform_data *priv;
struct resource *r;
@ -362,8 +361,7 @@ out:
return ret;
}
static int __devexit
i2c_platform_remove(struct platform_device *pdev)
static int i2c_platform_remove(struct platform_device *pdev)
{
struct i2c_platform_data *priv = platform_get_drvdata(pdev);
@ -408,7 +406,7 @@ static struct platform_driver i2c_platform_driver = {
.owner = THIS_MODULE,
},
.probe = i2c_platform_probe,
.remove = __devexit_p(i2c_platform_remove),
.remove = i2c_platform_remove,
.suspend = i2c_platform_suspend,
.resume = i2c_platform_resume,
};

8
arch/mips/pci/fixup-cobalt.c
View File

@ -37,7 +37,7 @@
#define VIA_COBALT_BRD_ID_REG 0x94
#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4)
static void __devinit qube_raq_galileo_early_fixup(struct pci_dev *dev)
static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
{
if (dev->devfn == PCI_DEVFN(0, 0) &&
(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
@ -51,7 +51,7 @@ static void __devinit qube_raq_galileo_early_fixup(struct pci_dev *dev)
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
qube_raq_galileo_early_fixup);
static void __devinit qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
{
unsigned short cfgword;
unsigned char lt;
@ -74,7 +74,7 @@ static void __devinit qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
qube_raq_via_bmIDE_fixup);
static void __devinit qube_raq_galileo_fixup(struct pci_dev *dev)
static void qube_raq_galileo_fixup(struct pci_dev *dev)
{
if (dev->devfn != PCI_DEVFN(0, 0))
return;
@ -129,7 +129,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
int cobalt_board_id;
static void __devinit qube_raq_via_board_id_fixup(struct pci_dev *dev)
static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
{
u8 id;
int retval;

4
arch/mips/pci/fixup-emma2rh.c
View File

@ -52,7 +52,7 @@ static unsigned char irq_map[][5] __initdata = {
MARKEINS_PCI_IRQ_INTA, MARKEINS_PCI_IRQ_INTB,},
};
static void __devinit nec_usb_controller_fixup(struct pci_dev *dev)
static void nec_usb_controller_fixup(struct pci_dev *dev)
{
if (PCI_SLOT(dev->devfn) == EMMA2RH_USB_SLOT)
/* on board USB controller configuration */
@ -67,7 +67,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
* if it is the host bridge by marking it as such. These resources are of
* no consequence to the PCI layer (they are handled elsewhere).
*/
static void __devinit emma2rh_pci_host_fixup(struct pci_dev *dev)
static void emma2rh_pci_host_fixup(struct pci_dev *dev)
{
int i;

12
arch/mips/pci/fixup-fuloong2e.c
View File

@ -48,7 +48,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
return 0;
}
static void __devinit loongson2e_nec_fixup(struct pci_dev *pdev)
static void loongson2e_nec_fixup(struct pci_dev *pdev)
{
unsigned int val;
@ -60,7 +60,7 @@ static void __devinit loongson2e_nec_fixup(struct pci_dev *pdev)
pci_write_config_dword(pdev, 0xe4, 1 << 5);
}
static void __devinit loongson2e_686b_func0_fixup(struct pci_dev *pdev)
static void loongson2e_686b_func0_fixup(struct pci_dev *pdev)
{
unsigned char c;
@ -135,7 +135,7 @@ static void __devinit loongson2e_686b_func0_fixup(struct pci_dev *pdev)
printk(KERN_INFO"via686b fix: ISA bridge done\n");
}
static void __devinit loongson2e_686b_func1_fixup(struct pci_dev *pdev)
static void loongson2e_686b_func1_fixup(struct pci_dev *pdev)
{
printk(KERN_INFO"via686b fix: IDE\n");
@ -168,19 +168,19 @@ static void __devinit loongson2e_686b_func1_fixup(struct pci_dev *pdev)
printk(KERN_INFO"via686b fix: IDE done\n");
}
static void __devinit loongson2e_686b_func2_fixup(struct pci_dev *pdev)
static void loongson2e_686b_func2_fixup(struct pci_dev *pdev)
{
/* irq routing */
pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10);
}
static void __devinit loongson2e_686b_func3_fixup(struct pci_dev *pdev)
static void loongson2e_686b_func3_fixup(struct pci_dev *pdev)
{
/* irq routing */
pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11);
}
static void __devinit loongson2e_686b_func5_fixup(struct pci_dev *pdev)
static void loongson2e_686b_func5_fixup(struct pci_dev *pdev)
{
unsigned int val;
unsigned char c;

12
arch/mips/pci/fixup-lemote2f.c
View File

@ -96,21 +96,21 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
}
/* CS5536 SPEC. fixup */
static void __devinit loongson_cs5536_isa_fixup(struct pci_dev *pdev)
static void loongson_cs5536_isa_fixup(struct pci_dev *pdev)
{
/* the uart1 and uart2 interrupt in PIC is enabled as default */
pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
}
static void __devinit loongson_cs5536_ide_fixup(struct pci_dev *pdev)
static void loongson_cs5536_ide_fixup(struct pci_dev *pdev)
{
/* setting the mutex pin as IDE function */
pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
CS5536_IDE_FLASH_SIGNATURE);
}
static void __devinit loongson_cs5536_acc_fixup(struct pci_dev *pdev)
static void loongson_cs5536_acc_fixup(struct pci_dev *pdev)
{
/* enable the AUDIO interrupt in PIC */
pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
@ -118,14 +118,14 @@ static void __devinit loongson_cs5536_acc_fixup(struct pci_dev *pdev)
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
}
static void __devinit loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
static void loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
{
/* enable the OHCI interrupt in PIC */
/* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
}
static void __devinit loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
static void loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
{
u32 hi, lo;
@ -137,7 +137,7 @@ static void __devinit loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
}
static void __devinit loongson_nec_fixup(struct pci_dev *pdev)
static void loongson_nec_fixup(struct pci_dev *pdev)
{
unsigned int val;

10
arch/mips/pci/fixup-malta.c
View File

@ -8,7 +8,7 @@
#define PCID 4
/* This table is filled in by interrogating the PIIX4 chip */
static char pci_irq[5] __devinitdata = {
static char pci_irq[5] = {
};
static char irq_tab[][5] __initdata = {
@ -50,10 +50,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
return 0;
}
static void __devinit malta_piix_func0_fixup(struct pci_dev *pdev)
static void malta_piix_func0_fixup(struct pci_dev *pdev)
{
unsigned char reg_val;
static int piixirqmap[16] __devinitdata = { /* PIIX PIRQC[A:D] irq mappings */
static int piixirqmap[16] = { /* PIIX PIRQC[A:D] irq mappings */
0, 0, 0, 3,
4, 5, 6, 7,
0, 9, 10, 11,
@ -84,7 +84,7 @@ static void __devinit malta_piix_func0_fixup(struct pci_dev *pdev)
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
malta_piix_func0_fixup);
static void __devinit malta_piix_func1_fixup(struct pci_dev *pdev)
static void malta_piix_func1_fixup(struct pci_dev *pdev)
{
unsigned char reg_val;
@ -104,7 +104,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
malta_piix_func1_fixup);
/* Enable PCI 2.1 compatibility in PIIX4 */
static void __devinit quirk_dlcsetup(struct pci_dev *dev)
static void quirk_dlcsetup(struct pci_dev *dev)
{
u8 odlc, ndlc;

6
arch/mips/pci/fixup-rc32434.c
View File

@ -32,12 +32,12 @@
#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/irq.h>
static int __devinitdata irq_map[2][12] = {
static int irq_map[2][12] = {
{0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
{0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3}
};
int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq = 0;
@ -47,7 +47,7 @@ int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
return irq + GROUP4_IRQ_BASE + 4;
}
static void __devinit rc32434_pci_early_fixup(struct pci_dev *dev)
static void rc32434_pci_early_fixup(struct pci_dev *dev)
{
if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
/* disable prefetched memory range */

6
arch/mips/pci/fixup-sb1250.c
View File

@ -15,7 +15,7 @@
* Set the BCM1250, etc. PCI host bridge's TRDY timeout
* to the finite max.
*/
static void __devinit quirk_sb1250_pci(struct pci_dev *dev)
static void quirk_sb1250_pci(struct pci_dev *dev)
{
pci_write_config_byte(dev, 0x40, 0xff);
}
@ -25,7 +25,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
/*
* The BCM1250, etc. PCI/HT bridge reports as a host bridge.
*/
static void __devinit quirk_sb1250_ht(struct pci_dev *dev)
static void quirk_sb1250_ht(struct pci_dev *dev)
{
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
}
@ -35,7 +35,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
/*
* Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max.
*/
static void __devinit quirk_sp1011(struct pci_dev *dev)
static void quirk_sp1011(struct pci_dev *dev)
{
pci_write_config_byte(dev, 0x64, 0xff);
}

2
arch/mips/pci/ops-bcm63xx.c
View File

@ -411,7 +411,7 @@ struct pci_ops bcm63xx_cb_ops = {
* only one IO window, so it cannot be shared by PCI and cardbus, use
* fixup to choose and detect unhandled configuration
*/
static void __devinit bcm63xx_fixup(struct pci_dev *dev)
static void bcm63xx_fixup(struct pci_dev *dev)
{
static int io_window = -1;
int i, found, new_io_window;

6
arch/mips/pci/ops-tx4927.c
View File

@ -191,13 +191,13 @@ static struct {
u8 trdyto;
u8 retryto;
u16 gbwc;
} tx4927_pci_opts __devinitdata = {
} tx4927_pci_opts = {
.trdyto = 0,
.retryto = 0,
.gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
};
char *__devinit tx4927_pcibios_setup(char *str)
char *tx4927_pcibios_setup(char *str)
{
unsigned long val;
@ -495,7 +495,7 @@ irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
}
#ifdef CONFIG_TOSHIBA_FPCIB0
static void __devinit tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
static void tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
{
struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);

2
arch/mips/pci/pci-alchemy.c
View File

@ -356,7 +356,7 @@ static struct syscore_ops alchemy_pci_pmops = {
.resume = alchemy_pci_resume,
};
static int __devinit alchemy_pci_probe(struct platform_device *pdev)
static int alchemy_pci_probe(struct platform_device *pdev)
{
struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
struct alchemy_pci_context *ctx;

4
arch/mips/pci/pci-ip27.c
View File

@ -143,7 +143,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
* A given PCI device, in general, should be able to intr any of the cpus
* on any one of the hubs connected to its xbow.
*/
int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return 0;
}
@ -212,7 +212,7 @@ static inline void pci_enable_swapping(struct pci_dev *dev)
bridge->b_widget.w_tflush; /* Flush */
}
static void __devinit pci_fixup_ioc3(struct pci_dev *d)
static void pci_fixup_ioc3(struct pci_dev *d)
{
pci_disable_swapping(d);
}

4
arch/mips/pci/pci-lantiq.c
View File

@ -95,7 +95,7 @@ static inline u32 ltq_calc_bar11mask(void)
return bar11mask;
}
static int __devinit ltq_pci_startup(struct platform_device *pdev)
static int ltq_pci_startup(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
const __be32 *req_mask, *bus_clk;
@ -201,7 +201,7 @@ static int __devinit ltq_pci_startup(struct platform_device *pdev)
return 0;
}
static int __devinit ltq_pci_probe(struct platform_device *pdev)
static int ltq_pci_probe(struct platform_device *pdev)
{
struct resource *res_cfg, *res_bridge;

9
arch/mips/pci/pci.c
View File

@ -76,7 +76,7 @@ pcibios_align_resource(void *data, const struct resource *res,
return start;
}
static void __devinit pcibios_scanbus(struct pci_controller *hose)
static void pcibios_scanbus(struct pci_controller *hose)
{
static int next_busno;
static int need_domain_info;
@ -120,8 +120,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
}
#ifdef CONFIG_OF
void __devinit pci_load_of_ranges(struct pci_controller *hose,
struct device_node *node)
void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
{
const __be32 *ranges;
int rlen;
@ -174,7 +173,7 @@ void __devinit pci_load_of_ranges(struct pci_controller *hose,
static DEFINE_MUTEX(pci_scan_mutex);
void __devinit register_pci_controller(struct pci_controller *hose)
void register_pci_controller(struct pci_controller *hose)
{
if (request_resource(&iomem_resource, hose->mem_resource) < 0)
goto out;
@ -303,7 +302,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
return pcibios_plat_dev_init(dev);
}
void __devinit pcibios_fixup_bus(struct pci_bus *bus)
void pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_dev *dev = bus->self;

2
arch/mips/sni/setup.c
View File

@ -236,7 +236,7 @@ void __init plat_mem_setup(void)
#include <video/vga.h>
#include <video/cirrus.h>
static void __devinit quirk_cirrus_ram_size(struct pci_dev *dev)
static void quirk_cirrus_ram_size(struct pci_dev *dev)
{
u16 cmd;

11
arch/mips/txx9/generic/pci.c
View File

@ -256,8 +256,7 @@ static irqreturn_t i8259_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
static int __devinit
txx9_i8259_irq_setup(int irq)
static int txx9_i8259_irq_setup(int irq)
{
int err;
@ -269,7 +268,7 @@ txx9_i8259_irq_setup(int irq)
return err;
}
static void __devinit quirk_slc90e66_bridge(struct pci_dev *dev)
static void quirk_slc90e66_bridge(struct pci_dev *dev)
{
int irq; /* PCI/ISA Bridge interrupt */
u8 reg_64;
@ -304,7 +303,7 @@ static void __devinit quirk_slc90e66_bridge(struct pci_dev *dev)
smsc_fdc37m81x_config_end();
}
static void __devinit quirk_slc90e66_ide(struct pci_dev *dev)
static void quirk_slc90e66_ide(struct pci_dev *dev)
{
unsigned char dat;
int regs[2] = {0x41, 0x43};
@ -339,7 +338,7 @@ static void __devinit quirk_slc90e66_ide(struct pci_dev *dev)
}
#endif /* CONFIG_TOSHIBA_FPCIB0 */
static void __devinit tc35815_fixup(struct pci_dev *dev)
static void tc35815_fixup(struct pci_dev *dev)
{
/* This device may have PM registers but not they are not supported. */
if (dev->pm_cap) {
@ -348,7 +347,7 @@ static void __devinit tc35815_fixup(struct pci_dev *dev)
}
}
static void __devinit final_fixup(struct pci_dev *dev)
static void final_fixup(struct pci_dev *dev)
{
unsigned char bist;