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ARM: dts: fix L2 address in Hi3620

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Fix the address of L2 controler register in hi3620 SoC.
This has been wrong from the point that the file was merged
in v3.14.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Cc: stable@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Haojian Zhuang 2014-04-02 21:31:50 +08:00 committed by Arnd Bergmann
parent bf1d9879ea
commit 28c9770bcb
1 changed files with 1 additions and 1 deletions
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arch/arm/boot/dts/hi3620.dtsi
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@ -73,7 +73,7 @@
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0xfc10000 0x100000>;
reg = <0x100000 0x100000>;
interrupts = <0 15 4>;
cache-unified;
cache-level = <2>;