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net: hns3: fix incorrect configuration for igu_egu_hw_err
According to the UM, the type and enable status of igu_egu_hw_err
should be configured separately. Currently, the type field is
incorrect when disable this error. So fix it by configuring these
two fields separately.
Fixes: bf1faf9415
("net: hns3: Add enable and process hw errors from IGU, EGU and NCSI")
Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -753,8 +753,9 @@ static int hclge_config_igu_egu_hw_err_int(struct hclge_dev *hdev, bool en)
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/* configure IGU,EGU error interrupts */
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/* configure IGU,EGU error interrupts */
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hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_COMMON_INT_EN, false);
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hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_COMMON_INT_EN, false);
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desc.data[0] = cpu_to_le32(HCLGE_IGU_ERR_INT_TYPE);
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if (en)
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if (en)
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desc.data[0] = cpu_to_le32(HCLGE_IGU_ERR_INT_EN);
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desc.data[0] |= cpu_to_le32(HCLGE_IGU_ERR_INT_EN);
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desc.data[1] = cpu_to_le32(HCLGE_IGU_ERR_INT_EN_MASK);
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desc.data[1] = cpu_to_le32(HCLGE_IGU_ERR_INT_EN_MASK);
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@ -32,7 +32,8 @@
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#define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
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#define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
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#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
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#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
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#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
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#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
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#define HCLGE_IGU_ERR_INT_EN 0x0000066F
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#define HCLGE_IGU_ERR_INT_EN 0x0000000F
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#define HCLGE_IGU_ERR_INT_TYPE 0x00000660
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#define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
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#define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
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#define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
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#define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
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#define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
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#define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
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