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ARM: EXYNOS: Add clock support for G-Scaler

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Add required clock support for G-Scaler for exynos5

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Prathyush K <prathyush.k@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Shaik Ameer Basha 2012-09-07 14:13:08 +09:00 committed by Kukjin Kim
parent 4cbe5a555f
commit 2822d3187b
1 changed files with 86 additions and 0 deletions
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86
arch/arm/mach-exynos/clock-exynos5.c
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@ -552,6 +552,68 @@ static struct clksrc_clk exynos5_clk_aclk_66 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
};
static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
.clk = {
.name = "mout_aclk_300_gscl_mid",
},
.sources = &exynos5_clkset_aclk,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
};
static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
[0] = &exynos5_clk_sclk_vpll.clk,
[1] = &exynos5_clk_mout_cpll.clk,
};
static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
.sources = exynos5_clkset_aclk_300_mid1_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
};
static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
.clk = {
.name = "mout_aclk_300_gscl_mid1",
},
.sources = &exynos5_clkset_aclk_300_gscl_mid1,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
};
static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
[0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
[1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
};
static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
.sources = exynos5_clkset_aclk_300_gscl_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
};
static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
.clk = {
.name = "mout_aclk_300_gscl",
},
.sources = &exynos5_clkset_aclk_300_gscl,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
};
static struct clk *exynos5_clk_src_gscl_300_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &exynos5_clk_mout_aclk_300_gscl.clk,
};
static struct clksrc_sources exynos5_clk_src_gscl_300 = {
.sources = exynos5_clk_src_gscl_300_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
};
static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
.clk = {
.name = "aclk_300_gscl",
},
.sources = &exynos5_clk_src_gscl_300,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
};
static struct clk exynos5_init_clocks_off[] = {
{
.name = "timers",
@ -763,6 +825,26 @@ static struct clk exynos5_init_clocks_off[] = {
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "gscl",
.devname = "exynos-gsc.0",
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "gscl",
.devname = "exynos-gsc.1",
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "gscl",
.devname = "exynos-gsc.2",
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "gscl",
.devname = "exynos-gsc.3",
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
@ -1225,6 +1307,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_aclk_266,
&exynos5_clk_aclk_200,
&exynos5_clk_aclk_166,
&exynos5_clk_aclk_300_gscl,
&exynos5_clk_mout_aclk_300_gscl,
&exynos5_clk_mout_aclk_300_gscl_mid,
&exynos5_clk_mout_aclk_300_gscl_mid1,
&exynos5_clk_aclk_66_pre,
&exynos5_clk_aclk_66,
&exynos5_clk_dout_mmc0,