mirror of
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msm: add gpio driver for single-core SoCs.
Install a gpiolib driver supporting the on-chip gpios for single-core MSMs in the 7x00 family, including 7x00A, 7x25, 7x27, 7x30, 8x50, and 8x50a. As part of the ongoing effort to converge on a common code base, this driver is based on the Google-Android msmgpio driver, whose authors include Brian Swetland and Arve Hjønnevåg. Cc: Arve Hjønnevåg <arve@android.com> Cc: H Hartley Sweeten <hartleys@visionengravers.com> Cc: Ryan Mallon <ryan@bluewatersys.com> Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
This commit is contained in:
Gregory Bean
Daniel Walker
parent
ab78cde589
commit
2783cc265c
@ -22,3 +22,6 @@ obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
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obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
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obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
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obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
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ifndef CONFIG_MSM_V2_TLMM
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obj-y += gpio.o
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endif
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358
arch/arm/mach-msm/gpio.c
Normal file
358
arch/arm/mach-msm/gpio.c
Normal file
@ -0,0 +1,358 @@
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/* linux/arch/arm/mach-msm/gpio.c
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/bitops.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include "gpio_hw.h"
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#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
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#define MSM_GPIO_BANK(bank, first, last) \
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{ \
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.regs = { \
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.out = MSM_GPIO_OUT_##bank, \
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.in = MSM_GPIO_IN_##bank, \
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.int_status = MSM_GPIO_INT_STATUS_##bank, \
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.int_clear = MSM_GPIO_INT_CLEAR_##bank, \
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.int_en = MSM_GPIO_INT_EN_##bank, \
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.int_edge = MSM_GPIO_INT_EDGE_##bank, \
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.int_pos = MSM_GPIO_INT_POS_##bank, \
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.oe = MSM_GPIO_OE_##bank, \
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}, \
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.chip = { \
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.base = (first), \
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.ngpio = (last) - (first) + 1, \
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.get = msm_gpio_get, \
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.set = msm_gpio_set, \
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.direction_input = msm_gpio_direction_input, \
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.direction_output = msm_gpio_direction_output, \
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.to_irq = msm_gpio_to_irq, \
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} \
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}
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#define MSM_GPIO_BROKEN_INT_CLEAR 1
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struct msm_gpio_regs {
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void __iomem *out;
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void __iomem *in;
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void __iomem *int_status;
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void __iomem *int_clear;
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void __iomem *int_en;
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void __iomem *int_edge;
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void __iomem *int_pos;
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void __iomem *oe;
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};
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struct msm_gpio_chip {
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spinlock_t lock;
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struct gpio_chip chip;
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struct msm_gpio_regs regs;
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#if MSM_GPIO_BROKEN_INT_CLEAR
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unsigned int_status_copy;
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#endif
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unsigned int both_edge_detect;
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unsigned int int_enable[2]; /* 0: awake, 1: sleep */
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};
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static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
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unsigned offset, unsigned on)
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{
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unsigned mask = BIT(offset);
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unsigned val;
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val = readl(msm_chip->regs.out);
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if (on)
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writel(val | mask, msm_chip->regs.out);
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else
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writel(val & ~mask, msm_chip->regs.out);
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return 0;
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}
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static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
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{
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int loop_limit = 100;
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unsigned pol, val, val2, intstat;
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do {
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val = readl(msm_chip->regs.in);
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pol = readl(msm_chip->regs.int_pos);
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pol = (pol & ~msm_chip->both_edge_detect) |
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(~val & msm_chip->both_edge_detect);
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writel(pol, msm_chip->regs.int_pos);
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intstat = readl(msm_chip->regs.int_status);
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val2 = readl(msm_chip->regs.in);
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if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
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return;
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} while (loop_limit-- > 0);
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printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
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"failed to reach stable state %x != %x\n", val, val2);
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}
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static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
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unsigned offset)
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{
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unsigned bit = BIT(offset);
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#if MSM_GPIO_BROKEN_INT_CLEAR
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/* Save interrupts that already triggered before we loose them. */
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/* Any interrupt that triggers between the read of int_status */
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/* and the write to int_clear will still be lost though. */
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msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
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msm_chip->int_status_copy &= ~bit;
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#endif
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writel(bit, msm_chip->regs.int_clear);
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msm_gpio_update_both_edge_detect(msm_chip);
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return 0;
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}
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static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct msm_gpio_chip *msm_chip;
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unsigned long irq_flags;
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msm_chip = container_of(chip, struct msm_gpio_chip, chip);
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spin_lock_irqsave(&msm_chip->lock, irq_flags);
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writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
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spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
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return 0;
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}
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static int
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msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct msm_gpio_chip *msm_chip;
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unsigned long irq_flags;
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msm_chip = container_of(chip, struct msm_gpio_chip, chip);
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spin_lock_irqsave(&msm_chip->lock, irq_flags);
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msm_gpio_write(msm_chip, offset, value);
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writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
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spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
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return 0;
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}
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static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct msm_gpio_chip *msm_chip;
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msm_chip = container_of(chip, struct msm_gpio_chip, chip);
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return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
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}
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static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct msm_gpio_chip *msm_chip;
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unsigned long irq_flags;
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msm_chip = container_of(chip, struct msm_gpio_chip, chip);
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spin_lock_irqsave(&msm_chip->lock, irq_flags);
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msm_gpio_write(msm_chip, offset, value);
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spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
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}
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static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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return MSM_GPIO_TO_INT(chip->base + offset);
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}
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struct msm_gpio_chip msm_gpio_chips[] = {
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#if defined(CONFIG_ARCH_MSM7X00A)
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MSM_GPIO_BANK(0, 0, 15),
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MSM_GPIO_BANK(1, 16, 42),
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MSM_GPIO_BANK(2, 43, 67),
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MSM_GPIO_BANK(3, 68, 94),
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MSM_GPIO_BANK(4, 95, 106),
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MSM_GPIO_BANK(5, 107, 121),
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#elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27)
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MSM_GPIO_BANK(0, 0, 15),
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MSM_GPIO_BANK(1, 16, 42),
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MSM_GPIO_BANK(2, 43, 67),
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MSM_GPIO_BANK(3, 68, 94),
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MSM_GPIO_BANK(4, 95, 106),
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MSM_GPIO_BANK(5, 107, 132),
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#elif defined(CONFIG_ARCH_MSM7X30)
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MSM_GPIO_BANK(0, 0, 15),
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MSM_GPIO_BANK(1, 16, 43),
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MSM_GPIO_BANK(2, 44, 67),
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MSM_GPIO_BANK(3, 68, 94),
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MSM_GPIO_BANK(4, 95, 106),
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MSM_GPIO_BANK(5, 107, 133),
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MSM_GPIO_BANK(6, 134, 150),
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MSM_GPIO_BANK(7, 151, 181),
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#elif defined(CONFIG_ARCH_QSD8X50)
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MSM_GPIO_BANK(0, 0, 15),
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MSM_GPIO_BANK(1, 16, 42),
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MSM_GPIO_BANK(2, 43, 67),
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MSM_GPIO_BANK(3, 68, 94),
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MSM_GPIO_BANK(4, 95, 103),
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MSM_GPIO_BANK(5, 104, 121),
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MSM_GPIO_BANK(6, 122, 152),
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MSM_GPIO_BANK(7, 153, 164),
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#endif
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};
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static void msm_gpio_irq_ack(unsigned int irq)
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{
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unsigned long irq_flags;
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struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
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spin_lock_irqsave(&msm_chip->lock, irq_flags);
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msm_gpio_clear_detect_status(msm_chip,
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irq - gpio_to_irq(msm_chip->chip.base));
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spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
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}
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static void msm_gpio_irq_mask(unsigned int irq)
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{
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unsigned long irq_flags;
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struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
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unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
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spin_lock_irqsave(&msm_chip->lock, irq_flags);
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/* level triggered interrupts are also latched */
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if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
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msm_gpio_clear_detect_status(msm_chip, offset);
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msm_chip->int_enable[0] &= ~BIT(offset);
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writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
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spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
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}
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static void msm_gpio_irq_unmask(unsigned int irq)
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{
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unsigned long irq_flags;
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struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
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unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
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spin_lock_irqsave(&msm_chip->lock, irq_flags);
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/* level triggered interrupts are also latched */
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if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
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msm_gpio_clear_detect_status(msm_chip, offset);
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msm_chip->int_enable[0] |= BIT(offset);
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writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
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spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
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}
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static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
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{
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unsigned long irq_flags;
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struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
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unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
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spin_lock_irqsave(&msm_chip->lock, irq_flags);
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if (on)
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msm_chip->int_enable[1] |= BIT(offset);
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else
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msm_chip->int_enable[1] &= ~BIT(offset);
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spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
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return 0;
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}
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static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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unsigned long irq_flags;
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struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
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unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
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unsigned val, mask = BIT(offset);
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spin_lock_irqsave(&msm_chip->lock, irq_flags);
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val = readl(msm_chip->regs.int_edge);
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if (flow_type & IRQ_TYPE_EDGE_BOTH) {
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writel(val | mask, msm_chip->regs.int_edge);
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irq_desc[irq].handle_irq = handle_edge_irq;
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} else {
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writel(val & ~mask, msm_chip->regs.int_edge);
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irq_desc[irq].handle_irq = handle_level_irq;
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}
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if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
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msm_chip->both_edge_detect |= mask;
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msm_gpio_update_both_edge_detect(msm_chip);
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} else {
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msm_chip->both_edge_detect &= ~mask;
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val = readl(msm_chip->regs.int_pos);
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
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writel(val | mask, msm_chip->regs.int_pos);
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else
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writel(val & ~mask, msm_chip->regs.int_pos);
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}
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spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
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return 0;
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}
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static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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int i, j, mask;
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unsigned val;
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for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
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struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
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val = readl(msm_chip->regs.int_status);
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val &= msm_chip->int_enable[0];
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while (val) {
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mask = val & -val;
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j = fls(mask) - 1;
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/* printk("%s %08x %08x bit %d gpio %d irq %d\n",
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__func__, v, m, j, msm_chip->chip.start + j,
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FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
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val &= ~mask;
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generic_handle_irq(FIRST_GPIO_IRQ +
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msm_chip->chip.base + j);
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}
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}
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desc->chip->ack(irq);
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}
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static struct irq_chip msm_gpio_irq_chip = {
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.name = "msmgpio",
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.ack = msm_gpio_irq_ack,
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.mask = msm_gpio_irq_mask,
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.unmask = msm_gpio_irq_unmask,
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.set_wake = msm_gpio_irq_set_wake,
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.set_type = msm_gpio_irq_set_type,
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};
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static int __init msm_init_gpio(void)
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{
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int i, j = 0;
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for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
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if (i - FIRST_GPIO_IRQ >=
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msm_gpio_chips[j].chip.base +
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msm_gpio_chips[j].chip.ngpio)
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j++;
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set_irq_chip_data(i, &msm_gpio_chips[j]);
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set_irq_chip(i, &msm_gpio_irq_chip);
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set_irq_handler(i, handle_edge_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
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spin_lock_init(&msm_gpio_chips[i].lock);
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writel(0, msm_gpio_chips[i].regs.int_en);
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gpiochip_add(&msm_gpio_chips[i].chip);
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}
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set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
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set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
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set_irq_wake(INT_GPIO_GROUP1, 1);
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set_irq_wake(INT_GPIO_GROUP2, 2);
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return 0;
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}
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postcore_initcall(msm_init_gpio);
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278
arch/arm/mach-msm/gpio_hw.h
Normal file
278
arch/arm/mach-msm/gpio_hw.h
Normal file
@ -0,0 +1,278 @@
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/* arch/arm/mach-msm/gpio_hw.h
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*
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* Copyright (C) 2007 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H
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#define __ARCH_ARM_MACH_MSM_GPIO_HW_H
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#include <mach/msm_iomap.h>
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/* see 80-VA736-2 Rev C pp 695-751
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**
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** These are actually the *shadow* gpio registers, since the
|
||||
** real ones (which allow full access) are only available to the
|
||||
** ARM9 side of the world.
|
||||
**
|
||||
** Since the _BASE need to be page-aligned when we're mapping them
|
||||
** to virtual addresses, adjust for the additional offset in these
|
||||
** macros.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_MSM7X30)
|
||||
#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
|
||||
#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
|
||||
#else
|
||||
#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
|
||||
#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\
|
||||
defined(CONFIG_ARCH_MSM7X27)
|
||||
|
||||
/* output value */
|
||||
#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
|
||||
#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
|
||||
#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
|
||||
#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
|
||||
#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
|
||||
#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */
|
||||
|
||||
/* same pin map as above, output enable */
|
||||
#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
|
||||
#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
|
||||
#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
|
||||
#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
|
||||
#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
|
||||
#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
|
||||
|
||||
/* same pin map as above, input read */
|
||||
#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
|
||||
#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
|
||||
#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
|
||||
#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
|
||||
#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
|
||||
#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
|
||||
|
||||
/* same pin map as above, 1=edge 0=level interrup */
|
||||
#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
|
||||
#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
|
||||
#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
|
||||
#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
|
||||
#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
|
||||
#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
|
||||
|
||||
/* same pin map as above, 1=positive 0=negative */
|
||||
#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
|
||||
#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
|
||||
#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
|
||||
#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
|
||||
#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
|
||||
#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
|
||||
|
||||
/* same pin map as above, interrupt enable */
|
||||
#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
|
||||
#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
|
||||
#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
|
||||
#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
|
||||
#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
|
||||
#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
|
||||
|
||||
/* same pin map as above, write 1 to clear interrupt */
|
||||
#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
|
||||
#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
|
||||
#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
|
||||
#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
|
||||
#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
|
||||
#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
|
||||
|
||||
/* same pin map as above, 1=interrupt pending */
|
||||
#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
|
||||
#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
|
||||
#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
|
||||
#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
|
||||
#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
|
||||
#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_QSD8X50)
|
||||
/* output value */
|
||||
#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
|
||||
#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
|
||||
#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
|
||||
#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
|
||||
#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 103-95 */
|
||||
#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x10) /* gpio 121-104 */
|
||||
#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0x14) /* gpio 152-122 */
|
||||
#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x18) /* gpio 164-153 */
|
||||
|
||||
/* same pin map as above, output enable */
|
||||
#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x20)
|
||||
#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
|
||||
#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x24)
|
||||
#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x28)
|
||||
#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x2C)
|
||||
#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x30)
|
||||
#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0x34)
|
||||
#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x38)
|
||||
|
||||
/* same pin map as above, input read */
|
||||
#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x50)
|
||||
#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
|
||||
#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x54)
|
||||
#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x58)
|
||||
#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x5C)
|
||||
#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x60)
|
||||
#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0x64)
|
||||
#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x68)
|
||||
|
||||
/* same pin map as above, 1=edge 0=level interrup */
|
||||
#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x70)
|
||||
#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
|
||||
#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x74)
|
||||
#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x78)
|
||||
#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x7C)
|
||||
#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0x80)
|
||||
#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0x84)
|
||||
#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x88)
|
||||
|
||||
/* same pin map as above, 1=positive 0=negative */
|
||||
#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x90)
|
||||
#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
|
||||
#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x94)
|
||||
#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x98)
|
||||
#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x9C)
|
||||
#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xA0)
|
||||
#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xA4)
|
||||
#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0xA8)
|
||||
|
||||
/* same pin map as above, interrupt enable */
|
||||
#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0xB0)
|
||||
#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
|
||||
#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0xB4)
|
||||
#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0xB8)
|
||||
#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0xBC)
|
||||
#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xC0)
|
||||
#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xC4)
|
||||
#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0xC8)
|
||||
|
||||
/* same pin map as above, write 1 to clear interrupt */
|
||||
#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0xD0)
|
||||
#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
|
||||
#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0xD4)
|
||||
#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0xD8)
|
||||
#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0xDC)
|
||||
#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xE0)
|
||||
#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xE4)
|
||||
#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0xE8)
|
||||
|
||||
/* same pin map as above, 1=interrupt pending */
|
||||
#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xF0)
|
||||
#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
|
||||
#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xF4)
|
||||
#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xF8)
|
||||
#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xFC)
|
||||
#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0x100)
|
||||
#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0x104)
|
||||
#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x108)
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_MSM7X30)
|
||||
|
||||
/* output value */
|
||||
#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
|
||||
#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
|
||||
#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
|
||||
#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
|
||||
#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
|
||||
#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
|
||||
#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
|
||||
#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
|
||||
|
||||
/* same pin map as above, output enable */
|
||||
#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
|
||||
#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
|
||||
#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
|
||||
#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
|
||||
#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
|
||||
#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
|
||||
#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
|
||||
#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x218)
|
||||
|
||||
/* same pin map as above, input read */
|
||||
#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
|
||||
#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
|
||||
#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
|
||||
#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
|
||||
#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
|
||||
#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
|
||||
#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
|
||||
#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
|
||||
|
||||
/* same pin map as above, 1=edge 0=level interrup */
|
||||
#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
|
||||
#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
|
||||
#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
|
||||
#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
|
||||
#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
|
||||
#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
|
||||
#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
|
||||
#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
|
||||
|
||||
/* same pin map as above, 1=positive 0=negative */
|
||||
#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
|
||||
#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
|
||||
#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
|
||||
#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
|
||||
#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
|
||||
#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
|
||||
#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
|
||||
#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
|
||||
|
||||
/* same pin map as above, interrupt enable */
|
||||
#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
|
||||
#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
|
||||
#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
|
||||
#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
|
||||
#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
|
||||
#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
|
||||
#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
|
||||
#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
|
||||
|
||||
/* same pin map as above, write 1 to clear interrupt */
|
||||
#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
|
||||
#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
|
||||
#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
|
||||
#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
|
||||
#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
|
||||
#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
|
||||
#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
|
||||
#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
|
||||
|
||||
/* same pin map as above, 1=interrupt pending */
|
||||
#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
|
||||
#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
|
||||
#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
|
||||
#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
|
||||
#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
|
||||
#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
|
||||
#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
|
||||
#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user