mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-15 16:53:54 +08:00
cxl/core/port: Add switch port enumeration
So far the platorm level CXL resources have been enumerated by the cxl_acpi driver, and cxl_pci has gathered all the pre-requisite information it needs to fire up a cxl_mem driver. However, the first thing the cxl_mem driver will be tasked to do is validate that all the PCIe Switches in its ancestry also have CXL capabilities and an CXL.mem link established. Provide a common mechanism for a CXL.mem endpoint driver to enumerate all the ancestor CXL ports in the topology and validate CXL.mem connectivity. Multiple endpoints may end up racing to establish a shared port in the topology. This race is resolved via taking the device-lock on a parent CXL Port before establishing a new child. The winner of the race establishes the port, the loser simply registers its interest in the port via 'struct cxl_ep' place-holder reference. At endpoint teardown the same parent port lock is taken as 'struct cxl_ep' references are deleted. Last endpoint to drop its reference unregisters the port. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/164398731146.902644.1029761300481366248.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
cf1f6877b0
commit
2703c16c75
@ -130,21 +130,6 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
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return 0;
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}
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static struct cxl_dport *find_dport_by_dev(struct cxl_port *port, struct device *dev)
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{
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struct cxl_dport *dport;
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cxl_device_lock(&port->dev);
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list_for_each_entry(dport, &port->dports, list)
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if (dport->dport == dev) {
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cxl_device_unlock(&port->dev);
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return dport;
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}
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cxl_device_unlock(&port->dev);
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return NULL;
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}
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__mock struct acpi_device *to_cxl_host_bridge(struct device *host,
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struct device *dev)
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{
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@ -175,7 +160,7 @@ static int add_host_bridge_uport(struct device *match, void *arg)
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if (!bridge)
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return 0;
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dport = find_dport_by_dev(root_port, match);
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dport = cxl_find_dport_by_dev(root_port, match);
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if (!dport) {
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dev_dbg(host, "host bridge expected and not found\n");
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return 0;
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@ -7,6 +7,7 @@
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#include <linux/slab.h>
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#include <linux/idr.h>
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#include <cxlmem.h>
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#include <cxlpci.h>
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#include <cxl.h>
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#include "core.h"
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@ -265,10 +266,24 @@ struct cxl_decoder *to_cxl_decoder(struct device *dev)
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}
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EXPORT_SYMBOL_NS_GPL(to_cxl_decoder, CXL);
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static void cxl_ep_release(struct cxl_ep *ep)
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{
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if (!ep)
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return;
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list_del(&ep->list);
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put_device(ep->ep);
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kfree(ep);
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}
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static void cxl_port_release(struct device *dev)
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{
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struct cxl_port *port = to_cxl_port(dev);
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struct cxl_ep *ep, *_e;
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cxl_device_lock(dev);
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list_for_each_entry_safe(ep, _e, &port->endpoints, list)
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cxl_ep_release(ep);
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cxl_device_unlock(dev);
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ida_free(&cxl_port_ida, port->id);
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kfree(port);
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}
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@ -359,6 +374,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
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port->component_reg_phys = component_reg_phys;
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ida_init(&port->decoder_ida);
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INIT_LIST_HEAD(&port->dports);
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INIT_LIST_HEAD(&port->endpoints);
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device_initialize(dev);
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device_set_pm_not_required(dev);
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@ -457,25 +473,36 @@ int devm_cxl_register_pci_bus(struct device *host, struct device *uport,
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_register_pci_bus, CXL);
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static bool dev_is_cxl_root_child(struct device *dev)
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{
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struct cxl_port *port, *parent;
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if (!is_cxl_port(dev))
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return false;
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port = to_cxl_port(dev);
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if (is_cxl_root(port))
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return false;
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parent = to_cxl_port(port->dev.parent);
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if (is_cxl_root(parent))
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return true;
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return false;
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}
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/* Find a 2nd level CXL port that has a dport that is an ancestor of @match */
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static int match_root_child(struct device *dev, const void *match)
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{
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const struct device *iter = NULL;
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struct cxl_port *port, *parent;
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struct cxl_dport *dport;
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struct cxl_port *port;
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if (!is_cxl_port(dev))
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if (!dev_is_cxl_root_child(dev))
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return 0;
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port = to_cxl_port(dev);
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if (is_cxl_root(port))
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return 0;
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parent = to_cxl_port(port->dev.parent);
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if (!is_cxl_root(parent))
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return 0;
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cxl_device_lock(&port->dev);
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cxl_device_lock(dev);
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list_for_each_entry(dport, &port->dports, list) {
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iter = match;
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while (iter) {
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@ -485,7 +512,7 @@ static int match_root_child(struct device *dev, const void *match)
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}
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}
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out:
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cxl_device_unlock(&port->dev);
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cxl_device_unlock(dev);
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return !!iter;
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}
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@ -642,6 +669,388 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_dport, CXL);
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static struct cxl_ep *find_ep(struct cxl_port *port, struct device *ep_dev)
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{
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struct cxl_ep *ep;
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device_lock_assert(&port->dev);
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list_for_each_entry(ep, &port->endpoints, list)
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if (ep->ep == ep_dev)
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return ep;
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return NULL;
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}
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static int add_ep(struct cxl_port *port, struct cxl_ep *new)
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{
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struct cxl_ep *dup;
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cxl_device_lock(&port->dev);
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if (port->dead) {
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cxl_device_unlock(&port->dev);
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return -ENXIO;
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}
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dup = find_ep(port, new->ep);
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if (!dup)
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list_add_tail(&new->list, &port->endpoints);
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cxl_device_unlock(&port->dev);
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return dup ? -EEXIST : 0;
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}
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/**
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* cxl_add_ep - register an endpoint's interest in a port
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* @port: a port in the endpoint's topology ancestry
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* @ep_dev: device representing the endpoint
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*
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* Intermediate CXL ports are scanned based on the arrival of endpoints.
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* When those endpoints depart the port can be destroyed once all
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* endpoints that care about that port have been removed.
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*/
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static int cxl_add_ep(struct cxl_port *port, struct device *ep_dev)
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{
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struct cxl_ep *ep;
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int rc;
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ep = kzalloc(sizeof(*ep), GFP_KERNEL);
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if (!ep)
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return -ENOMEM;
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INIT_LIST_HEAD(&ep->list);
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ep->ep = get_device(ep_dev);
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rc = add_ep(port, ep);
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if (rc)
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cxl_ep_release(ep);
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return rc;
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}
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struct cxl_find_port_ctx {
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const struct device *dport_dev;
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const struct cxl_port *parent_port;
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};
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static int match_port_by_dport(struct device *dev, const void *data)
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{
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const struct cxl_find_port_ctx *ctx = data;
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struct cxl_port *port;
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if (!is_cxl_port(dev))
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return 0;
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if (ctx->parent_port && dev->parent != &ctx->parent_port->dev)
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return 0;
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port = to_cxl_port(dev);
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return cxl_find_dport_by_dev(port, ctx->dport_dev) != NULL;
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}
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static struct cxl_port *__find_cxl_port(struct cxl_find_port_ctx *ctx)
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{
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struct device *dev;
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if (!ctx->dport_dev)
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return NULL;
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dev = bus_find_device(&cxl_bus_type, NULL, ctx, match_port_by_dport);
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if (dev)
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return to_cxl_port(dev);
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return NULL;
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}
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static struct cxl_port *find_cxl_port(struct device *dport_dev)
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{
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struct cxl_find_port_ctx ctx = {
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.dport_dev = dport_dev,
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};
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return __find_cxl_port(&ctx);
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}
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static struct cxl_port *find_cxl_port_at(struct cxl_port *parent_port,
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struct device *dport_dev)
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{
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struct cxl_find_port_ctx ctx = {
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.dport_dev = dport_dev,
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.parent_port = parent_port,
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};
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return __find_cxl_port(&ctx);
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}
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/*
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* All users of grandparent() are using it to walk PCIe-like swich port
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* hierarchy. A PCIe switch is comprised of a bridge device representing the
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* upstream switch port and N bridges representing downstream switch ports. When
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* bridges stack the grand-parent of a downstream switch port is another
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* downstream switch port in the immediate ancestor switch.
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*/
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static struct device *grandparent(struct device *dev)
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{
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if (dev && dev->parent)
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return dev->parent->parent;
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return NULL;
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}
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/*
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* The natural end of life of a non-root 'cxl_port' is when its parent port goes
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* through a ->remove() event ("top-down" unregistration). The unnatural trigger
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* for a port to be unregistered is when all memdevs beneath that port have gone
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* through ->remove(). This "bottom-up" removal selectively removes individual
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* child ports manually. This depends on devm_cxl_add_port() to not change is
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* devm action registration order.
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*/
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static void delete_switch_port(struct cxl_port *port, struct list_head *dports)
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{
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struct cxl_dport *dport, *_d;
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list_for_each_entry_safe(dport, _d, dports, list) {
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devm_release_action(&port->dev, cxl_dport_unlink, dport);
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devm_release_action(&port->dev, cxl_dport_remove, dport);
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devm_kfree(&port->dev, dport);
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}
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devm_release_action(port->dev.parent, cxl_unlink_uport, port);
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devm_release_action(port->dev.parent, unregister_port, port);
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}
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static void cxl_detach_ep(void *data)
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{
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struct cxl_memdev *cxlmd = data;
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struct device *iter;
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for (iter = &cxlmd->dev; iter; iter = grandparent(iter)) {
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struct device *dport_dev = grandparent(iter);
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struct cxl_port *port, *parent_port;
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LIST_HEAD(reap_dports);
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struct cxl_ep *ep;
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if (!dport_dev)
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break;
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port = find_cxl_port(dport_dev);
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if (!port || is_cxl_root(port)) {
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put_device(&port->dev);
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continue;
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}
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parent_port = to_cxl_port(port->dev.parent);
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cxl_device_lock(&parent_port->dev);
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if (!parent_port->dev.driver) {
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/*
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* The bottom-up race to delete the port lost to a
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* top-down port disable, give up here, because the
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* parent_port ->remove() will have cleaned up all
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* descendants.
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*/
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cxl_device_unlock(&parent_port->dev);
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put_device(&port->dev);
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continue;
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}
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cxl_device_lock(&port->dev);
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ep = find_ep(port, &cxlmd->dev);
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dev_dbg(&cxlmd->dev, "disconnect %s from %s\n",
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ep ? dev_name(ep->ep) : "", dev_name(&port->dev));
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cxl_ep_release(ep);
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if (ep && !port->dead && list_empty(&port->endpoints) &&
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!is_cxl_root(parent_port)) {
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/*
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* This was the last ep attached to a dynamically
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* enumerated port. Block new cxl_add_ep() and garbage
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* collect the port.
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*/
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port->dead = true;
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list_splice_init(&port->dports, &reap_dports);
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}
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cxl_device_unlock(&port->dev);
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if (!list_empty(&reap_dports)) {
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dev_dbg(&cxlmd->dev, "delete %s\n",
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dev_name(&port->dev));
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delete_switch_port(port, &reap_dports);
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}
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put_device(&port->dev);
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cxl_device_unlock(&parent_port->dev);
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}
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}
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static resource_size_t find_component_registers(struct device *dev)
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{
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struct cxl_register_map map;
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struct pci_dev *pdev;
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/*
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* Theoretically, CXL component registers can be hosted on a
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* non-PCI device, in practice, only cxl_test hits this case.
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*/
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if (!dev_is_pci(dev))
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return CXL_RESOURCE_NONE;
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pdev = to_pci_dev(dev);
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cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
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return cxl_regmap_to_base(pdev, &map);
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}
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static int add_port_attach_ep(struct cxl_memdev *cxlmd,
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struct device *uport_dev,
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struct device *dport_dev)
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{
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struct device *dparent = grandparent(dport_dev);
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struct cxl_port *port, *parent_port = NULL;
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resource_size_t component_reg_phys;
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int rc;
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if (!dparent) {
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/*
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* The iteration reached the topology root without finding the
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* CXL-root 'cxl_port' on a previous iteration, fail for now to
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* be re-probed after platform driver attaches.
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*/
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dev_dbg(&cxlmd->dev, "%s is a root dport\n",
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dev_name(dport_dev));
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return -ENXIO;
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}
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parent_port = find_cxl_port(dparent);
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if (!parent_port) {
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/* iterate to create this parent_port */
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return -EAGAIN;
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}
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cxl_device_lock(&parent_port->dev);
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if (!parent_port->dev.driver) {
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dev_warn(&cxlmd->dev,
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"port %s:%s disabled, failed to enumerate CXL.mem\n",
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dev_name(&parent_port->dev), dev_name(uport_dev));
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port = ERR_PTR(-ENXIO);
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goto out;
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}
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port = find_cxl_port_at(parent_port, dport_dev);
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if (!port) {
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component_reg_phys = find_component_registers(uport_dev);
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port = devm_cxl_add_port(&parent_port->dev, uport_dev,
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component_reg_phys, parent_port);
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if (!IS_ERR(port))
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get_device(&port->dev);
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}
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out:
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cxl_device_unlock(&parent_port->dev);
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if (IS_ERR(port))
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rc = PTR_ERR(port);
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else {
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dev_dbg(&cxlmd->dev, "add to new port %s:%s\n",
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dev_name(&port->dev), dev_name(port->uport));
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rc = cxl_add_ep(port, &cxlmd->dev);
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if (rc == -EEXIST) {
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/*
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* "can't" happen, but this error code means
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* something to the caller, so translate it.
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*/
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rc = -ENXIO;
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}
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put_device(&port->dev);
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}
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put_device(&parent_port->dev);
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return rc;
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}
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int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
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{
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struct device *dev = &cxlmd->dev;
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struct device *iter;
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int rc;
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rc = devm_add_action_or_reset(&cxlmd->dev, cxl_detach_ep, cxlmd);
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if (rc)
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return rc;
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/*
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* Scan for and add all cxl_ports in this device's ancestry.
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* Repeat until no more ports are added. Abort if a port add
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* attempt fails.
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*/
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retry:
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for (iter = dev; iter; iter = grandparent(iter)) {
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struct device *dport_dev = grandparent(iter);
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struct device *uport_dev;
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struct cxl_port *port;
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if (!dport_dev)
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return 0;
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uport_dev = dport_dev->parent;
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if (!uport_dev) {
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dev_warn(dev, "at %s no parent for dport: %s\n",
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dev_name(iter), dev_name(dport_dev));
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return -ENXIO;
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}
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dev_dbg(dev, "scan: iter: %s dport_dev: %s parent: %s\n",
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dev_name(iter), dev_name(dport_dev),
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dev_name(uport_dev));
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port = find_cxl_port(dport_dev);
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if (port) {
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dev_dbg(&cxlmd->dev,
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||||
"found already registered port %s:%s\n",
|
||||
dev_name(&port->dev), dev_name(port->uport));
|
||||
rc = cxl_add_ep(port, &cxlmd->dev);
|
||||
|
||||
/*
|
||||
* If the endpoint already exists in the port's list,
|
||||
* that's ok, it was added on a previous pass.
|
||||
* Otherwise, retry in add_port_attach_ep() after taking
|
||||
* the parent_port lock as the current port may be being
|
||||
* reaped.
|
||||
*/
|
||||
if (rc && rc != -EEXIST) {
|
||||
put_device(&port->dev);
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Any more ports to add between this one and the root? */
|
||||
if (!dev_is_cxl_root_child(&port->dev)) {
|
||||
put_device(&port->dev);
|
||||
continue;
|
||||
}
|
||||
|
||||
put_device(&port->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
rc = add_port_attach_ep(cxlmd, uport_dev, dport_dev);
|
||||
/* port missing, try to add parent */
|
||||
if (rc == -EAGAIN)
|
||||
continue;
|
||||
/* failed to add ep or port */
|
||||
if (rc)
|
||||
return rc;
|
||||
/* port added, new descendants possible, start over */
|
||||
goto retry;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_ports, CXL);
|
||||
|
||||
struct cxl_dport *cxl_find_dport_by_dev(struct cxl_port *port,
|
||||
const struct device *dev)
|
||||
{
|
||||
struct cxl_dport *dport;
|
||||
|
||||
cxl_device_lock(&port->dev);
|
||||
list_for_each_entry(dport, &port->dports, list)
|
||||
if (dport->dport == dev) {
|
||||
cxl_device_unlock(&port->dev);
|
||||
return dport;
|
||||
}
|
||||
|
||||
cxl_device_unlock(&port->dev);
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(cxl_find_dport_by_dev, CXL);
|
||||
|
||||
static int decoder_populate_targets(struct cxl_decoder *cxld,
|
||||
struct cxl_port *port, int *target_map)
|
||||
{
|
||||
|
||||
@ -262,8 +262,10 @@ struct cxl_nvdimm {
|
||||
* @uport: PCI or platform device implementing the upstream port capability
|
||||
* @id: id for port device-name
|
||||
* @dports: cxl_dport instances referenced by decoders
|
||||
* @endpoints: cxl_ep instances, endpoints that are a descendant of this port
|
||||
* @decoder_ida: allocator for decoder ids
|
||||
* @component_reg_phys: component register capability base address (optional)
|
||||
* @dead: last ep has been removed, force port re-creation
|
||||
* @depth: How deep this port is relative to the root. depth 0 is the root.
|
||||
*/
|
||||
struct cxl_port {
|
||||
@ -271,8 +273,10 @@ struct cxl_port {
|
||||
struct device *uport;
|
||||
int id;
|
||||
struct list_head dports;
|
||||
struct list_head endpoints;
|
||||
struct ida decoder_ida;
|
||||
resource_size_t component_reg_phys;
|
||||
bool dead;
|
||||
unsigned int depth;
|
||||
};
|
||||
|
||||
@ -292,6 +296,16 @@ struct cxl_dport {
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct cxl_ep - track an endpoint's interest in a port
|
||||
* @ep: device that hosts a generic CXL endpoint (expander or accelerator)
|
||||
* @list: node on port->endpoints list
|
||||
*/
|
||||
struct cxl_ep {
|
||||
struct device *ep;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
/*
|
||||
* The platform firmware device hosting the root is also the top of the
|
||||
* CXL port topology. All other CXL ports have another CXL port as their
|
||||
@ -313,9 +327,14 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
|
||||
resource_size_t component_reg_phys,
|
||||
struct cxl_port *parent_port);
|
||||
struct cxl_port *find_cxl_root(struct device *dev);
|
||||
int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
|
||||
|
||||
struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
|
||||
struct device *dport, int port_id,
|
||||
resource_size_t component_reg_phys);
|
||||
struct cxl_dport *cxl_find_dport_by_dev(struct cxl_port *port,
|
||||
const struct device *dev);
|
||||
|
||||
struct cxl_decoder *to_cxl_decoder(struct device *dev);
|
||||
bool is_root_decoder(struct device *dev);
|
||||
bool is_cxl_decoder(struct device *dev);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user