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serial: sh-sci: Add more register documentation
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Simon Horman <horms@verge.net.au> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Geert Uytterhoeven
Greg Kroah-Hartman
parent
ff43da00e0
commit
26de4f1b2f
@ -911,7 +911,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
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/* Disable future Rx interrupts */
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if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
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disable_irq_nosync(irq);
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scr |= 0x4000;
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scr |= SCSCR_RDRQE;
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} else {
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scr &= ~SCSCR_RIE;
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}
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@ -1200,7 +1200,9 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
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*/
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reg = sci_getreg(port, SCFCR);
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if (reg->size)
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serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
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serial_port_out(port, SCFCR,
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serial_port_in(port, SCFCR) |
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SCFCR_LOOP);
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}
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}
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@ -1496,9 +1498,9 @@ static void sci_start_tx(struct uart_port *port)
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if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
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u16 new, scr = serial_port_in(port, SCSCR);
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if (s->chan_tx)
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new = scr | 0x8000;
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new = scr | SCSCR_TDRQE;
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else
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new = scr & ~0x8000;
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new = scr & ~SCSCR_TDRQE;
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if (new != scr)
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serial_port_out(port, SCSCR, new);
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}
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@ -1525,7 +1527,7 @@ static void sci_stop_tx(struct uart_port *port)
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ctrl = serial_port_in(port, SCSCR);
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if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
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ctrl &= ~0x8000;
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ctrl &= ~SCSCR_TDRQE;
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ctrl &= ~SCSCR_TIE;
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@ -1539,7 +1541,7 @@ static void sci_start_rx(struct uart_port *port)
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ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
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if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
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ctrl &= ~0x4000;
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ctrl &= ~SCSCR_RDRQE;
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serial_port_out(port, SCSCR, ctrl);
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}
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@ -1551,7 +1553,7 @@ static void sci_stop_rx(struct uart_port *port)
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ctrl = serial_port_in(port, SCSCR);
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if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
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ctrl &= ~0x4000;
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ctrl &= ~SCSCR_RDRQE;
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ctrl &= ~port_rx_irq_mask(port);
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@ -1614,7 +1616,7 @@ static void rx_timer_fn(unsigned long arg)
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u16 scr = serial_port_in(port, SCSCR);
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if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
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scr &= ~0x4000;
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scr &= ~SCSCR_RDRQE;
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enable_irq(s->irqs[SCIx_RXI_IRQ]);
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}
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serial_port_out(port, SCSCR, scr | SCSCR_RIE);
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@ -1871,13 +1873,13 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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smr_val = serial_port_in(port, SCSMR) & 3;
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if ((termios->c_cflag & CSIZE) == CS7)
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smr_val |= 0x40;
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smr_val |= SCSMR_CHR;
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if (termios->c_cflag & PARENB)
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smr_val |= 0x20;
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smr_val |= SCSMR_PE;
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if (termios->c_cflag & PARODD)
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smr_val |= 0x30;
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smr_val |= SCSMR_PE | SCSMR_ODD;
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if (termios->c_cflag & CSTOPB)
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smr_val |= 0x08;
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smr_val |= SCSMR_STOP;
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uart_update_timeout(port, termios->c_cflag, baud);
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@ -1885,7 +1887,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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__func__, smr_val, cks, t, s->cfg->scscr);
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if (t >= 0) {
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serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
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serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
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serial_port_out(port, SCBRR, t);
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reg = sci_getreg(port, HSSRR);
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if (reg->size)
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@ -10,45 +10,59 @@
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#define SCIx_NOT_SUPPORTED (-1)
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#define SCSCR_TIE (1 << 7)
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#define SCSCR_RIE (1 << 6)
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#define SCSCR_TE (1 << 5)
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#define SCSCR_RE (1 << 4)
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#define SCSCR_REIE (1 << 3) /* not supported by all parts */
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#define SCSCR_TOIE (1 << 2) /* not supported by all parts */
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#define SCSCR_CKE1 (1 << 1)
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#define SCSCR_CKE0 (1 << 0)
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/* SCSMR (Serial Mode Register) */
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#define SCSMR_CHR (1 << 6) /* 7-bit Character Length */
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#define SCSMR_PE (1 << 5) /* Parity Enable */
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#define SCSMR_ODD (1 << 4) /* Odd Parity */
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#define SCSMR_STOP (1 << 3) /* Stop Bit Length */
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#define SCSMR_CKS 0x0003 /* Clock Select */
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/* SCxSR SCI */
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#define SCI_TDRE 0x80
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#define SCI_RDRF 0x40
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#define SCI_ORER 0x20
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#define SCI_FER 0x10
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#define SCI_PER 0x08
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#define SCI_TEND 0x04
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/* Serial Control Register (@ = not supported by all parts) */
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#define SCSCR_TIE (1 << 7) /* Transmit Interrupt Enable */
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#define SCSCR_RIE (1 << 6) /* Receive Interrupt Enable */
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#define SCSCR_TE (1 << 5) /* Transmit Enable */
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#define SCSCR_RE (1 << 4) /* Receive Enable */
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#define SCSCR_REIE (1 << 3) /* Receive Error Interrupt Enable @ */
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#define SCSCR_TOIE (1 << 2) /* Timeout Interrupt Enable @ */
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#define SCSCR_CKE1 (1 << 1) /* Clock Enable 1 */
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#define SCSCR_CKE0 (1 << 0) /* Clock Enable 0 */
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/* SCIFA/SCIFB only */
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#define SCSCR_TDRQE (1 << 15) /* Tx Data Transfer Request Enable */
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#define SCSCR_RDRQE (1 << 14) /* Rx Data Transfer Request Enable */
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/* SCxSR (Serial Status Register) on SCI */
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#define SCI_TDRE 0x80 /* Transmit Data Register Empty */
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#define SCI_RDRF 0x40 /* Receive Data Register Full */
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#define SCI_ORER 0x20 /* Overrun Error */
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#define SCI_FER 0x10 /* Framing Error */
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#define SCI_PER 0x08 /* Parity Error */
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#define SCI_TEND 0x04 /* Transmit End */
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#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
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/* SCxSR SCIF, HSCIF */
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#define SCIF_ER 0x0080
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#define SCIF_TEND 0x0040
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#define SCIF_TDFE 0x0020
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#define SCIF_BRK 0x0010
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#define SCIF_FER 0x0008
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#define SCIF_PER 0x0004
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#define SCIF_RDF 0x0002
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#define SCIF_DR 0x0001
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/* SCxSR (Serial Status Register) on SCIF, HSCIF */
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#define SCIF_ER 0x0080 /* Receive Error */
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#define SCIF_TEND 0x0040 /* Transmission End */
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#define SCIF_TDFE 0x0020 /* Transmit FIFO Data Empty */
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#define SCIF_BRK 0x0010 /* Break Detect */
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#define SCIF_FER 0x0008 /* Framing Error */
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#define SCIF_PER 0x0004 /* Parity Error */
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#define SCIF_RDF 0x0002 /* Receive FIFO Data Full */
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#define SCIF_DR 0x0001 /* Receive Data Ready */
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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/* SCSPTR, optional */
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#define SCSPTR_RTSIO (1 << 7)
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#define SCSPTR_CTSIO (1 << 5)
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#define SCSPTR_SPB2IO (1 << 1)
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#define SCSPTR_SPB2DT (1 << 0)
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/* SCFCR (FIFO Control Register) */
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#define SCFCR_LOOP (1 << 0) /* Loopback Test */
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/* SCSPTR (Serial Port Register), optional */
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#define SCSPTR_RTSIO (1 << 7) /* Serial Port RTS Pin Input/Output */
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#define SCSPTR_CTSIO (1 << 5) /* Serial Port CTS Pin Input/Output */
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#define SCSPTR_SPB2IO (1 << 1) /* Serial Port Break Input/Output */
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#define SCSPTR_SPB2DT (1 << 0) /* Serial Port Break Data */
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/* HSSRR HSCIF */
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#define HSCIF_SRE 0x8000
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#define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */
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enum {
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SCIx_PROBE_REGTYPE,
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@ -73,10 +87,19 @@ enum {
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* Not all registers will exist on all parts.
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*/
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enum {
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SCSMR, SCBRR, SCSCR, SCxSR,
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SCFCR, SCFDR, SCxTDR, SCxRDR,
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SCLSR, SCTFDR, SCRFDR, SCSPTR,
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HSSRR,
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SCSMR, /* Serial Mode Register */
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SCBRR, /* Bit Rate Register */
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SCSCR, /* Serial Control Register */
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SCxSR, /* Serial Status Register */
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SCFCR, /* FIFO Control Register */
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SCFDR, /* FIFO Data Count Register */
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SCxTDR, /* Transmit (FIFO) Data Register */
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SCxRDR, /* Receive (FIFO) Data Register */
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SCLSR, /* Line Status Register */
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SCTFDR, /* Transmit FIFO Data Count Register */
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SCRFDR, /* Receive FIFO Data Count Register */
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SCSPTR, /* Serial Port Register */
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HSSRR, /* Sampling Rate Register */
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SCIx_NR_REGS,
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};
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