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include/asm-x86/sync_bitops.h: checkpatch cleanups - formatting only
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -13,7 +13,7 @@
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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*/
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#define ADDR (*(volatile long *) addr)
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#define ADDR (*(volatile long *)addr)
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/**
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* sync_set_bit - Atomically set a bit in memory
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@ -26,12 +26,12 @@
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void sync_set_bit(int nr, volatile unsigned long * addr)
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static inline void sync_set_bit(int nr, volatile unsigned long *addr)
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{
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__asm__ __volatile__("lock; btsl %1,%0"
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:"+m" (ADDR)
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:"Ir" (nr)
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: "memory");
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asm volatile("lock; btsl %1,%0"
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: "+m" (ADDR)
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: "Ir" (nr)
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: "memory");
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}
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/**
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@ -44,12 +44,12 @@ static inline void sync_set_bit(int nr, volatile unsigned long * addr)
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static inline void sync_clear_bit(int nr, volatile unsigned long * addr)
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static inline void sync_clear_bit(int nr, volatile unsigned long *addr)
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{
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__asm__ __volatile__("lock; btrl %1,%0"
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:"+m" (ADDR)
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:"Ir" (nr)
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: "memory");
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asm volatile("lock; btrl %1,%0"
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: "+m" (ADDR)
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: "Ir" (nr)
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: "memory");
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}
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/**
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@ -61,12 +61,12 @@ static inline void sync_clear_bit(int nr, volatile unsigned long * addr)
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void sync_change_bit(int nr, volatile unsigned long * addr)
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static inline void sync_change_bit(int nr, volatile unsigned long *addr)
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{
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__asm__ __volatile__("lock; btcl %1,%0"
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:"+m" (ADDR)
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:"Ir" (nr)
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: "memory");
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asm volatile("lock; btcl %1,%0"
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: "+m" (ADDR)
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: "Ir" (nr)
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: "memory");
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}
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/**
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@ -77,13 +77,13 @@ static inline void sync_change_bit(int nr, volatile unsigned long * addr)
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int sync_test_and_set_bit(int nr, volatile unsigned long * addr)
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static inline int sync_test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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int oldbit;
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__asm__ __volatile__("lock; btsl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"Ir" (nr) : "memory");
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asm volatile("lock; btsl %2,%1\n\tsbbl %0,%0"
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: "=r" (oldbit), "+m" (ADDR)
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: "Ir" (nr) : "memory");
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return oldbit;
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}
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@ -95,13 +95,13 @@ static inline int sync_test_and_set_bit(int nr, volatile unsigned long * addr)
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int sync_test_and_clear_bit(int nr, volatile unsigned long * addr)
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static inline int sync_test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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int oldbit;
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__asm__ __volatile__("lock; btrl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"Ir" (nr) : "memory");
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asm volatile("lock; btrl %2,%1\n\tsbbl %0,%0"
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: "=r" (oldbit), "+m" (ADDR)
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: "Ir" (nr) : "memory");
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return oldbit;
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}
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@ -113,13 +113,13 @@ static inline int sync_test_and_clear_bit(int nr, volatile unsigned long * addr)
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int sync_test_and_change_bit(int nr, volatile unsigned long* addr)
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static inline int sync_test_and_change_bit(int nr, volatile unsigned long *addr)
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{
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int oldbit;
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__asm__ __volatile__("lock; btcl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"Ir" (nr) : "memory");
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asm volatile("lock; btcl %2,%1\n\tsbbl %0,%0"
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: "=r" (oldbit), "+m" (ADDR)
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: "Ir" (nr) : "memory");
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return oldbit;
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}
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