mirror of
https://github.com/edk2-porting/linux-next.git
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Linux 3.19-rc7
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJUzvgKAAoJEHm+PkMAQRiG8XQH/1qVbHI4pP0KcnzfZUHq/mXq RuS4aJMwLm/Y6cXFraXBDaPde1A3CPtwtpob2C6giKcfu2zXGunY65haOEeJWNpX lCbBsLkNC3oDNkygBpVr5Zd6yibaw63WBjjLnpAi7pn2G2Zm2zB8DfILWWWMb7yz MH8ZXV+/xIYCTkjNWGWA1iMjmdYqu0PQHPeOgLsYQ+u7rxfM1zb/wHEkjqUZS6iu IaaZv7PV2PnFYnqib/iIPYjAEDvSQ4vN/7b82zlFd2Culm9j/568KCCWUPhJTb2l X0u4QYs49GnMTWVRa3bgYxS/nTUaE/6DeWs2y2WzqTt0/XDntVUnok0blUeDxGk= =o2kS -----END PGP SIGNATURE----- Merge tag 'v3.19-rc7' into locking/core, to refresh the branch before applying new changes Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
commit
2622e849a1
@ -14,3 +14,18 @@ Description:
|
||||
The /sys/class/mei/meiN directory is created for
|
||||
each probed mei device
|
||||
|
||||
What: /sys/class/mei/meiN/fw_status
|
||||
Date: Nov 2014
|
||||
KernelVersion: 3.19
|
||||
Contact: Tomas Winkler <tomas.winkler@intel.com>
|
||||
Description: Display fw status registers content
|
||||
|
||||
The ME FW writes its status information into fw status
|
||||
registers for BIOS and OS to monitor fw health.
|
||||
|
||||
The register contains running state, power management
|
||||
state, error codes, and others. The way the registers
|
||||
are decoded depends on PCH or SoC generation.
|
||||
Also number of registers varies between 1 and 6
|
||||
depending on generation.
|
||||
|
||||
|
||||
@ -1,60 +0,0 @@
|
||||
What: /sys/class/leds/dell::kbd_backlight/als_setting
|
||||
Date: December 2014
|
||||
KernelVersion: 3.19
|
||||
Contact: Gabriele Mazzotta <gabriele.mzt@gmail.com>,
|
||||
Pali Rohár <pali.rohar@gmail.com>
|
||||
Description:
|
||||
This file allows to control the automatic keyboard
|
||||
illumination mode on some systems that have an ambient
|
||||
light sensor. Write 1 to this file to enable the auto
|
||||
mode, 0 to disable it.
|
||||
|
||||
What: /sys/class/leds/dell::kbd_backlight/start_triggers
|
||||
Date: December 2014
|
||||
KernelVersion: 3.19
|
||||
Contact: Gabriele Mazzotta <gabriele.mzt@gmail.com>,
|
||||
Pali Rohár <pali.rohar@gmail.com>
|
||||
Description:
|
||||
This file allows to control the input triggers that
|
||||
turn on the keyboard backlight illumination that is
|
||||
disabled because of inactivity.
|
||||
Read the file to see the triggers available. The ones
|
||||
enabled are preceded by '+', those disabled by '-'.
|
||||
|
||||
To enable a trigger, write its name preceded by '+' to
|
||||
this file. To disable a trigger, write its name preceded
|
||||
by '-' instead.
|
||||
|
||||
For example, to enable the keyboard as trigger run:
|
||||
echo +keyboard > /sys/class/leds/dell::kbd_backlight/start_triggers
|
||||
To disable it:
|
||||
echo -keyboard > /sys/class/leds/dell::kbd_backlight/start_triggers
|
||||
|
||||
Note that not all the available triggers can be configured.
|
||||
|
||||
What: /sys/class/leds/dell::kbd_backlight/stop_timeout
|
||||
Date: December 2014
|
||||
KernelVersion: 3.19
|
||||
Contact: Gabriele Mazzotta <gabriele.mzt@gmail.com>,
|
||||
Pali Rohár <pali.rohar@gmail.com>
|
||||
Description:
|
||||
This file allows to specify the interval after which the
|
||||
keyboard illumination is disabled because of inactivity.
|
||||
The timeouts are expressed in seconds, minutes, hours and
|
||||
days, for which the symbols are 's', 'm', 'h' and 'd'
|
||||
respectively.
|
||||
|
||||
To configure the timeout, write to this file a value along
|
||||
with any the above units. If no unit is specified, the value
|
||||
is assumed to be expressed in seconds.
|
||||
|
||||
For example, to set the timeout to 10 minutes run:
|
||||
echo 10m > /sys/class/leds/dell::kbd_backlight/stop_timeout
|
||||
|
||||
Note that when this file is read, the returned value might be
|
||||
expressed in a different unit than the one used when the timeout
|
||||
was set.
|
||||
|
||||
Also note that only some timeouts are supported and that
|
||||
some systems might fall back to a specific timeout in case
|
||||
an invalid timeout is written to this file.
|
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@ -23,7 +23,7 @@ Required nodes:
|
||||
range of 0x200 bytes.
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|
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- syscon: the root node of the Integrator platforms must have a
|
||||
system controller node pointong to the control registers,
|
||||
system controller node pointing to the control registers,
|
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with the compatible string
|
||||
"arm,integrator-ap-syscon"
|
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"arm,integrator-cp-syscon"
|
||||
|
||||
72
Documentation/devicetree/bindings/arm/fw-cfg.txt
Normal file
72
Documentation/devicetree/bindings/arm/fw-cfg.txt
Normal file
@ -0,0 +1,72 @@
|
||||
* QEMU Firmware Configuration bindings for ARM
|
||||
|
||||
QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets
|
||||
provide the following Firmware Configuration interface on the "virt" machine
|
||||
type:
|
||||
|
||||
- A write-only, 16-bit wide selector (or control) register,
|
||||
- a read-write, 64-bit wide data register.
|
||||
|
||||
QEMU exposes the control and data register to ARM guests as memory mapped
|
||||
registers; their location is communicated to the guest's UEFI firmware in the
|
||||
DTB that QEMU places at the bottom of the guest's DRAM.
|
||||
|
||||
The guest writes a selector value (a key) to the selector register, and then
|
||||
can read the corresponding data (produced by QEMU) via the data register. If
|
||||
the selected entry is writable, the guest can rewrite it through the data
|
||||
register.
|
||||
|
||||
The selector register takes keys in big endian byte order.
|
||||
|
||||
The data register allows accesses with 8, 16, 32 and 64-bit width (only at
|
||||
offset 0 of the register). Accesses larger than a byte are interpreted as
|
||||
arrays, bundled together only for better performance. The bytes constituting
|
||||
such a word, in increasing address order, correspond to the bytes that would
|
||||
have been transferred by byte-wide accesses in chronological order.
|
||||
|
||||
The interface allows guest firmware to download various parameters and blobs
|
||||
that affect how the firmware works and what tables it installs for the guest
|
||||
OS. For example, boot order of devices, ACPI tables, SMBIOS tables, kernel and
|
||||
initrd images for direct kernel booting, virtual machine UUID, SMP information,
|
||||
virtual NUMA topology, and so on.
|
||||
|
||||
The authoritative registry of the valid selector values and their meanings is
|
||||
the QEMU source code; the structure of the data blobs corresponding to the
|
||||
individual key values is also defined in the QEMU source code.
|
||||
|
||||
The presence of the registers can be verified by selecting the "signature" blob
|
||||
with key 0x0000, and reading four bytes from the data register. The returned
|
||||
signature is "QEMU".
|
||||
|
||||
The outermost protocol (involving the write / read sequences of the control and
|
||||
data registers) is expected to be versioned, and/or described by feature bits.
|
||||
The interface revision / feature bitmap can be retrieved with key 0x0001. The
|
||||
blob to be read from the data register has size 4, and it is to be interpreted
|
||||
as a uint32_t value in little endian byte order. The current value
|
||||
(corresponding to the above outer protocol) is zero.
|
||||
|
||||
The guest kernel is not expected to use these registers (although it is
|
||||
certainly allowed to); the device tree bindings are documented here because
|
||||
this is where device tree bindings reside in general.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "qemu,fw-cfg-mmio".
|
||||
|
||||
- reg: the MMIO region used by the device.
|
||||
* Bytes 0x0 to 0x7 cover the data register.
|
||||
* Bytes 0x8 to 0x9 cover the selector register.
|
||||
* Further registers may be appended to the region in case of future interface
|
||||
revisions / feature bits.
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
fw-cfg@9020000 {
|
||||
compatible = "qemu,fw-cfg-mmio";
|
||||
reg = <0x0 0x9020000 0x0 0xa>;
|
||||
};
|
||||
};
|
||||
@ -19,7 +19,7 @@ type of the connections, they just map their existence. Specific properties
|
||||
may be described by specialized bindings depending on the type of connection.
|
||||
|
||||
To see how this binding applies to video pipelines, for example, see
|
||||
Documentation/device-tree/bindings/media/video-interfaces.txt.
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
Here the ports describe data interfaces, and the links between them are
|
||||
the connecting data buses. A single port with multiple connections can
|
||||
correspond to multiple devices being connected to the same physical bus.
|
||||
|
||||
@ -31,7 +31,7 @@ i2c0: i2c@fed40000 {
|
||||
compatible = "st,comms-ssc4-i2c";
|
||||
reg = <0xfed40000 0x110>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&CLK_S_ICN_REG_0>;
|
||||
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
|
||||
clock-names = "ssc";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -47,6 +47,7 @@ dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM
|
||||
dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
|
||||
dallas,ds75 Digital Thermometer and Thermostat
|
||||
dlg,da9053 DA9053: flexible system level PMIC with multicore support
|
||||
dlg,da9063 DA9063: system PMIC for quad-core application processors
|
||||
epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE
|
||||
epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
|
||||
fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
|
||||
|
||||
@ -4,7 +4,8 @@ This file provides information, what the device node
|
||||
for the davinci_emac interface contains.
|
||||
|
||||
Required properties:
|
||||
- compatible: "ti,davinci-dm6467-emac" or "ti,am3517-emac"
|
||||
- compatible: "ti,davinci-dm6467-emac", "ti,am3517-emac" or
|
||||
"ti,dm816-emac"
|
||||
- reg: Offset and length of the register set for the device
|
||||
- ti,davinci-ctrl-reg-offset: offset to control register
|
||||
- ti,davinci-ctrl-mod-reg-offset: offset to control module register
|
||||
|
||||
@ -9,7 +9,6 @@ ad Avionic Design GmbH
|
||||
adapteva Adapteva, Inc.
|
||||
adi Analog Devices, Inc.
|
||||
aeroflexgaisler Aeroflex Gaisler AB
|
||||
ak Asahi Kasei Corp.
|
||||
allwinner Allwinner Technology Co., Ltd.
|
||||
altr Altera Corp.
|
||||
amcc Applied Micro Circuits Corporation (APM, formally AMCC)
|
||||
@ -20,6 +19,7 @@ amstaos AMS-Taos Inc.
|
||||
apm Applied Micro Circuits Corporation (APM)
|
||||
arm ARM Ltd.
|
||||
armadeus ARMadeus Systems SARL
|
||||
asahi-kasei Asahi Kasei Corp.
|
||||
atmel Atmel Corporation
|
||||
auo AU Optronics Corporation
|
||||
avago Avago Technologies
|
||||
@ -127,6 +127,7 @@ pixcir PIXCIR MICROELECTRONICS Co., Ltd
|
||||
powervr PowerVR (deprecated, use img)
|
||||
qca Qualcomm Atheros, Inc.
|
||||
qcom Qualcomm Technologies, Inc
|
||||
qemu QEMU, a generic and open source machine emulator and virtualizer
|
||||
qnap QNAP Systems, Inc.
|
||||
radxa Radxa
|
||||
raidsonic RaidSonic Technology GmbH
|
||||
@ -168,6 +169,7 @@ usi Universal Scientific Industrial Co., Ltd.
|
||||
v3 V3 Semiconductor
|
||||
variscite Variscite Ltd.
|
||||
via VIA Technologies, Inc.
|
||||
virtio Virtual I/O Device Specification, developed by the OASIS consortium
|
||||
voipac Voipac Technologies s.r.o.
|
||||
winbond Winbond Electronics corp.
|
||||
wlf Wolfson Microelectronics
|
||||
|
||||
@ -1277,6 +1277,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
||||
i8042.notimeout [HW] Ignore timeout condition signalled by controller
|
||||
i8042.reset [HW] Reset the controller during init and cleanup
|
||||
i8042.unlock [HW] Unlock (ignore) the keylock
|
||||
i8042.kbdreset [HW] Reset device connected to KBD port
|
||||
|
||||
i810= [HW,DRM]
|
||||
|
||||
|
||||
@ -66,6 +66,8 @@ fwmark_reflect - BOOLEAN
|
||||
route/max_size - INTEGER
|
||||
Maximum number of routes allowed in the kernel. Increase
|
||||
this when using large numbers of interfaces and/or routes.
|
||||
From linux kernel 3.6 onwards, this is deprecated for ipv4
|
||||
as route cache is no longer used.
|
||||
|
||||
neigh/default/gc_thresh1 - INTEGER
|
||||
Minimum number of entries to keep. Garbage collector will not
|
||||
|
||||
@ -3,7 +3,7 @@ CPU cooling APIs How To
|
||||
|
||||
Written by Amit Daniel Kachhap <amit.kachhap@linaro.org>
|
||||
|
||||
Updated: 12 May 2012
|
||||
Updated: 6 Jan 2015
|
||||
|
||||
Copyright (c) 2012 Samsung Electronics Co., Ltd(http://www.samsung.com)
|
||||
|
||||
@ -25,7 +25,18 @@ the user. The registration APIs returns the cooling device pointer.
|
||||
|
||||
clip_cpus: cpumask of cpus where the frequency constraints will happen.
|
||||
|
||||
1.1.2 void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev)
|
||||
1.1.2 struct thermal_cooling_device *of_cpufreq_cooling_register(
|
||||
struct device_node *np, const struct cpumask *clip_cpus)
|
||||
|
||||
This interface function registers the cpufreq cooling device with
|
||||
the name "thermal-cpufreq-%x" linking it with a device tree node, in
|
||||
order to bind it via the thermal DT code. This api can support multiple
|
||||
instances of cpufreq cooling devices.
|
||||
|
||||
np: pointer to the cooling device device tree node
|
||||
clip_cpus: cpumask of cpus where the frequency constraints will happen.
|
||||
|
||||
1.1.3 void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev)
|
||||
|
||||
This interface function unregisters the "thermal-cpufreq-%x" cooling device.
|
||||
|
||||
|
||||
119
MAINTAINERS
119
MAINTAINERS
@ -696,7 +696,7 @@ L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
W: http://blackfin.uclinux.org/
|
||||
S: Supported
|
||||
F: sound/soc/blackfin/*
|
||||
|
||||
|
||||
ANALOG DEVICES INC IIO DRIVERS
|
||||
M: Lars-Peter Clausen <lars@metafoo.de>
|
||||
M: Michael Hennerich <Michael.Hennerich@analog.com>
|
||||
@ -708,6 +708,16 @@ X: drivers/iio/*/adjd*
|
||||
F: drivers/staging/iio/*/ad*
|
||||
F: staging/iio/trigger/iio-trig-bfin-timer.c
|
||||
|
||||
ANDROID DRIVERS
|
||||
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
M: Arve Hjønnevåg <arve@android.com>
|
||||
M: Riley Andrews <riandrews@android.com>
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/gregkh/staging.git
|
||||
L: devel@driverdev.osuosl.org
|
||||
S: Supported
|
||||
F: drivers/android/
|
||||
F: drivers/staging/android/
|
||||
|
||||
AOA (Apple Onboard Audio) ALSA DRIVER
|
||||
M: Johannes Berg <johannes@sipsolutions.net>
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
@ -754,13 +764,6 @@ L: linux-media@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/media/i2c/aptina-pll.*
|
||||
|
||||
ARASAN COMPACT FLASH PATA CONTROLLER
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: linux-ide@vger.kernel.org
|
||||
S: Maintained
|
||||
F: include/linux/pata_arasan_cf_data.h
|
||||
F: drivers/ata/pata_arasan_cf.c
|
||||
|
||||
ARC FRAMEBUFFER DRIVER
|
||||
M: Jaya Kumar <jayalk@intworks.biz>
|
||||
S: Maintained
|
||||
@ -2346,7 +2349,8 @@ CAN NETWORK LAYER
|
||||
M: Oliver Hartkopp <socketcan@hartkopp.net>
|
||||
L: linux-can@vger.kernel.org
|
||||
W: http://gitorious.org/linux-can
|
||||
T: git git://gitorious.org/linux-can/linux-can-next.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next.git
|
||||
S: Maintained
|
||||
F: Documentation/networking/can.txt
|
||||
F: net/can/
|
||||
@ -2361,7 +2365,8 @@ M: Wolfgang Grandegger <wg@grandegger.com>
|
||||
M: Marc Kleine-Budde <mkl@pengutronix.de>
|
||||
L: linux-can@vger.kernel.org
|
||||
W: http://gitorious.org/linux-can
|
||||
T: git git://gitorious.org/linux-can/linux-can-next.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next.git
|
||||
S: Maintained
|
||||
F: drivers/net/can/
|
||||
F: include/linux/can/dev.h
|
||||
@ -3183,7 +3188,7 @@ L: dmaengine@vger.kernel.org
|
||||
Q: https://patchwork.kernel.org/project/linux-dmaengine/list/
|
||||
S: Maintained
|
||||
F: drivers/dma/
|
||||
F: include/linux/dma*
|
||||
F: include/linux/dmaengine.h
|
||||
F: Documentation/dmaengine/
|
||||
T: git git://git.infradead.org/users/vkoul/slave-dma.git
|
||||
|
||||
@ -4749,20 +4754,20 @@ S: Supported
|
||||
F: drivers/scsi/ipr.*
|
||||
|
||||
IBM Power Virtual Ethernet Device Driver
|
||||
M: Santiago Leon <santil@linux.vnet.ibm.com>
|
||||
M: Thomas Falcon <tlfalcon@linux.vnet.ibm.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/net/ethernet/ibm/ibmveth.*
|
||||
|
||||
IBM Power Virtual SCSI Device Drivers
|
||||
M: Nathan Fontenot <nfont@linux.vnet.ibm.com>
|
||||
M: Tyrel Datwyler <tyreld@linux.vnet.ibm.com>
|
||||
L: linux-scsi@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/scsi/ibmvscsi/ibmvscsi*
|
||||
F: drivers/scsi/ibmvscsi/viosrp.h
|
||||
|
||||
IBM Power Virtual FC Device Drivers
|
||||
M: Brian King <brking@linux.vnet.ibm.com>
|
||||
M: Tyrel Datwyler <tyreld@linux.vnet.ibm.com>
|
||||
L: linux-scsi@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/scsi/ibmvscsi/ibmvfc*
|
||||
@ -4930,7 +4935,6 @@ F: include/uapi/linux/inotify.h
|
||||
|
||||
INPUT (KEYBOARD, MOUSE, JOYSTICK, TOUCHSCREEN) DRIVERS
|
||||
M: Dmitry Torokhov <dmitry.torokhov@gmail.com>
|
||||
M: Dmitry Torokhov <dtor@mail.ru>
|
||||
L: linux-input@vger.kernel.org
|
||||
Q: http://patchwork.kernel.org/project/linux-input/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git
|
||||
@ -4952,7 +4956,6 @@ K: \b(ABS|SYN)_MT_
|
||||
INTEL C600 SERIES SAS CONTROLLER DRIVER
|
||||
M: Intel SCU Linux support <intel-linux-scu@intel.com>
|
||||
M: Artur Paszkiewicz <artur.paszkiewicz@intel.com>
|
||||
M: Dave Jiang <dave.jiang@intel.com>
|
||||
L: linux-scsi@vger.kernel.org
|
||||
T: git git://git.code.sf.net/p/intel-sas/isci
|
||||
S: Supported
|
||||
@ -5703,6 +5706,49 @@ F: drivers/lguest/
|
||||
F: include/linux/lguest*.h
|
||||
F: tools/lguest/
|
||||
|
||||
LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)
|
||||
M: Tejun Heo <tj@kernel.org>
|
||||
L: linux-ide@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git
|
||||
S: Maintained
|
||||
F: drivers/ata/
|
||||
F: include/linux/ata.h
|
||||
F: include/linux/libata.h
|
||||
|
||||
LIBATA PATA ARASAN COMPACT FLASH CONTROLLER
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: linux-ide@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git
|
||||
S: Maintained
|
||||
F: include/linux/pata_arasan_cf_data.h
|
||||
F: drivers/ata/pata_arasan_cf.c
|
||||
|
||||
LIBATA PATA DRIVERS
|
||||
M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
|
||||
M: Tejun Heo <tj@kernel.org>
|
||||
L: linux-ide@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git
|
||||
S: Maintained
|
||||
F: drivers/ata/pata_*.c
|
||||
F: drivers/ata/ata_generic.c
|
||||
|
||||
LIBATA SATA AHCI PLATFORM devices support
|
||||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
M: Tejun Heo <tj@kernel.org>
|
||||
L: linux-ide@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git
|
||||
S: Maintained
|
||||
F: drivers/ata/ahci_platform.c
|
||||
F: drivers/ata/libahci_platform.c
|
||||
F: include/linux/ahci_platform.h
|
||||
|
||||
LIBATA SATA PROMISE TX2/TX4 CONTROLLER DRIVER
|
||||
M: Mikael Pettersson <mikpelinux@gmail.com>
|
||||
L: linux-ide@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git
|
||||
S: Maintained
|
||||
F: drivers/ata/sata_promise.*
|
||||
|
||||
LIBLOCKDEP
|
||||
M: Sasha Levin <sasha.levin@oracle.com>
|
||||
S: Maintained
|
||||
@ -6987,14 +7033,12 @@ OPEN FIRMWARE AND FLATTENED DEVICE TREE
|
||||
M: Grant Likely <grant.likely@linaro.org>
|
||||
M: Rob Herring <robh+dt@kernel.org>
|
||||
L: devicetree@vger.kernel.org
|
||||
W: http://fdt.secretlab.ca
|
||||
T: git git://git.secretlab.ca/git/linux-2.6.git
|
||||
W: http://www.devicetree.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux.git
|
||||
S: Maintained
|
||||
F: drivers/of/
|
||||
F: include/linux/of*.h
|
||||
F: scripts/dtc/
|
||||
K: of_get_property
|
||||
K: of_match_table
|
||||
|
||||
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
|
||||
M: Rob Herring <robh+dt@kernel.org>
|
||||
@ -7239,7 +7283,7 @@ S: Maintained
|
||||
F: drivers/pci/host/*layerscape*
|
||||
|
||||
PCI DRIVER FOR IMX6
|
||||
M: Richard Zhu <r65037@freescale.com>
|
||||
M: Richard Zhu <Richard.Zhu@freescale.com>
|
||||
M: Lucas Stach <l.stach@pengutronix.de>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
@ -7409,6 +7453,7 @@ F: drivers/crypto/picoxcell*
|
||||
PIN CONTROL SUBSYSTEM
|
||||
M: Linus Walleij <linus.walleij@linaro.org>
|
||||
L: linux-gpio@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
|
||||
S: Maintained
|
||||
F: drivers/pinctrl/
|
||||
F: include/linux/pinctrl/
|
||||
@ -7576,12 +7621,6 @@ W: http://wireless.kernel.org/en/users/Drivers/p54
|
||||
S: Obsolete
|
||||
F: drivers/net/wireless/prism54/
|
||||
|
||||
PROMISE SATA TX2/TX4 CONTROLLER LIBATA DRIVER
|
||||
M: Mikael Pettersson <mikpelinux@gmail.com>
|
||||
L: linux-ide@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/ata/sata_promise.*
|
||||
|
||||
PS3 NETWORK SUPPORT
|
||||
M: Geoff Levand <geoff@infradead.org>
|
||||
L: netdev@vger.kernel.org
|
||||
@ -7747,8 +7786,7 @@ F: Documentation/scsi/LICENSE.qla2xxx
|
||||
F: drivers/scsi/qla2xxx/
|
||||
|
||||
QLOGIC QLA4XXX iSCSI DRIVER
|
||||
M: Vikas Chaudhary <vikas.chaudhary@qlogic.com>
|
||||
M: iscsi-driver@qlogic.com
|
||||
M: QLogic-Storage-Upstream@qlogic.com
|
||||
L: linux-scsi@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/scsi/LICENSE.qla4xxx
|
||||
@ -8556,25 +8594,6 @@ S: Maintained
|
||||
F: drivers/misc/phantom.c
|
||||
F: include/uapi/linux/phantom.h
|
||||
|
||||
SERIAL ATA (SATA) SUBSYSTEM
|
||||
M: Tejun Heo <tj@kernel.org>
|
||||
L: linux-ide@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git
|
||||
S: Supported
|
||||
F: drivers/ata/
|
||||
F: include/linux/ata.h
|
||||
F: include/linux/libata.h
|
||||
|
||||
SERIAL ATA AHCI PLATFORM devices support
|
||||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
M: Tejun Heo <tj@kernel.org>
|
||||
L: linux-ide@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git
|
||||
S: Supported
|
||||
F: drivers/ata/ahci_platform.c
|
||||
F: drivers/ata/libahci_platform.c
|
||||
F: include/linux/ahci_platform.h
|
||||
|
||||
SERVER ENGINES 10Gbps iSCSI - BladeEngine 2 DRIVER
|
||||
M: Jayamohan Kallickal <jayamohan.kallickal@emulex.com>
|
||||
L: linux-scsi@vger.kernel.org
|
||||
@ -9543,7 +9562,8 @@ F: drivers/platform/x86/thinkpad_acpi.c
|
||||
TI BANDGAP AND THERMAL DRIVER
|
||||
M: Eduardo Valentin <edubezval@gmail.com>
|
||||
L: linux-pm@vger.kernel.org
|
||||
S: Supported
|
||||
L: linux-omap@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/thermal/ti-soc-thermal/
|
||||
|
||||
TI CLOCK DRIVER
|
||||
@ -10156,6 +10176,7 @@ USERSPACE I/O (UIO)
|
||||
M: "Hans J. Koch" <hjk@hansjkoch.de>
|
||||
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
|
||||
F: Documentation/DocBook/uio-howto.tmpl
|
||||
F: drivers/uio/
|
||||
F: include/linux/uio*.h
|
||||
|
||||
2
Makefile
2
Makefile
@ -1,7 +1,7 @@
|
||||
VERSION = 3
|
||||
PATCHLEVEL = 19
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc4
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Diseased Newt
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
||||
@ -285,8 +285,12 @@ pcibios_claim_one_bus(struct pci_bus *b)
|
||||
if (r->parent || !r->start || !r->flags)
|
||||
continue;
|
||||
if (pci_has_flag(PCI_PROBE_ONLY) ||
|
||||
(r->flags & IORESOURCE_PCI_FIXED))
|
||||
pci_claim_resource(dev, i);
|
||||
(r->flags & IORESOURCE_PCI_FIXED)) {
|
||||
if (pci_claim_resource(dev, i) == 0)
|
||||
continue;
|
||||
|
||||
pci_claim_bridge_resource(dev, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -156,6 +156,8 @@ retry:
|
||||
if (unlikely(fault & VM_FAULT_ERROR)) {
|
||||
if (fault & VM_FAULT_OOM)
|
||||
goto out_of_memory;
|
||||
else if (fault & VM_FAULT_SIGSEGV)
|
||||
goto bad_area;
|
||||
else if (fault & VM_FAULT_SIGBUS)
|
||||
goto do_sigbus;
|
||||
BUG();
|
||||
|
||||
@ -161,6 +161,8 @@ good_area:
|
||||
|
||||
if (fault & VM_FAULT_OOM)
|
||||
goto out_of_memory;
|
||||
else if (fault & VM_FAULT_SIGSEGV)
|
||||
goto bad_area;
|
||||
else if (fault & VM_FAULT_SIGBUS)
|
||||
goto do_sigbus;
|
||||
|
||||
|
||||
@ -953,6 +953,8 @@
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fb>;
|
||||
clocks = <&lcd_clk>, <&lcd_clk>;
|
||||
clock-names = "lcdc_clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -65,6 +65,8 @@
|
||||
};
|
||||
|
||||
&sdhci2 {
|
||||
broken-cd;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -83,7 +83,8 @@
|
||||
compatible = "mrvl,pxav3-mmc";
|
||||
reg = <0xab1000 0x200>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&chip CLKID_SDIO1XIN>;
|
||||
clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
|
||||
clock-names = "io", "core";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -348,36 +349,6 @@
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio4: gpio@5000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x5000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-port@4 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio5: gpio@c000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xc000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portf: gpio-port@5 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chip: chip-control@ea0000 {
|
||||
@ -466,6 +437,21 @@
|
||||
ranges = <0 0xfc0000 0x10000>;
|
||||
interrupt-parent = <&sic>;
|
||||
|
||||
sm_gpio1: gpio@5000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x5000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portf: gpio-port@5 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2: i2c@7000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
#address-cells = <1>;
|
||||
@ -516,6 +502,21 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sm_gpio0: gpio@c000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xc000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-port@4 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sysctrl: pin-controller@d000 {
|
||||
compatible = "marvell,berlin2q-system-ctrl";
|
||||
reg = <0xd000 0x100>;
|
||||
|
||||
@ -499,23 +499,23 @@
|
||||
};
|
||||
partition@5 {
|
||||
label = "QSPI.u-boot-spl-os";
|
||||
reg = <0x00140000 0x00010000>;
|
||||
reg = <0x00140000 0x00080000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "QSPI.u-boot-env";
|
||||
reg = <0x00150000 0x00010000>;
|
||||
reg = <0x001c0000 0x00010000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "QSPI.u-boot-env.backup1";
|
||||
reg = <0x00160000 0x0010000>;
|
||||
reg = <0x001d0000 0x0010000>;
|
||||
};
|
||||
partition@8 {
|
||||
label = "QSPI.kernel";
|
||||
reg = <0x00170000 0x0800000>;
|
||||
reg = <0x001e0000 0x0800000>;
|
||||
};
|
||||
partition@9 {
|
||||
label = "QSPI.file-system";
|
||||
reg = <0x00970000 0x01690000>;
|
||||
reg = <0x009e0000 0x01620000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -1257,6 +1257,8 @@
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "super-speed";
|
||||
dr_mode = "otg";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1278,6 +1280,8 @@
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1299,6 +1303,8 @@
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -736,7 +736,7 @@
|
||||
|
||||
dp_phy: video-phy@10040720 {
|
||||
compatible = "samsung,exynos5250-dp-video-phy";
|
||||
reg = <0x10040720 4>;
|
||||
samsung,pmu-syscon = <&pmu_system_controller>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
@ -372,3 +372,7 @@
|
||||
&usbdrd_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cci {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -120,7 +120,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
cci@10d20000 {
|
||||
cci: cci@10d20000 {
|
||||
compatible = "arm,cci-400";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -503,8 +503,8 @@
|
||||
};
|
||||
|
||||
dp_phy: video-phy@10040728 {
|
||||
compatible = "samsung,exynos5250-dp-video-phy";
|
||||
reg = <0x10040728 4>;
|
||||
compatible = "samsung,exynos5420-dp-video-phy";
|
||||
samsung,pmu-syscon = <&pmu_system_controller>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
@ -162,7 +162,7 @@
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
|
||||
reg = <0x43fa4000 0x4000>;
|
||||
clocks = <&clks 62>, <&clks 62>;
|
||||
clocks = <&clks 78>, <&clks 78>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <14>;
|
||||
status = "disabled";
|
||||
@ -369,7 +369,7 @@
|
||||
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
|
||||
#pwm-cells = <2>;
|
||||
reg = <0x53fa0000 0x4000>;
|
||||
clocks = <&clks 106>, <&clks 36>;
|
||||
clocks = <&clks 106>, <&clks 52>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <36>;
|
||||
};
|
||||
@ -388,7 +388,7 @@
|
||||
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
|
||||
#pwm-cells = <2>;
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
clocks = <&clks 107>, <&clks 36>;
|
||||
clocks = <&clks 107>, <&clks 52>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <41>;
|
||||
};
|
||||
@ -429,7 +429,7 @@
|
||||
pwm4: pwm@53fc8000 {
|
||||
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
clocks = <&clks 108>, <&clks 36>;
|
||||
clocks = <&clks 108>, <&clks 52>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <42>;
|
||||
};
|
||||
@ -476,7 +476,7 @@
|
||||
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
|
||||
#pwm-cells = <2>;
|
||||
reg = <0x53fe0000 0x4000>;
|
||||
clocks = <&clks 105>, <&clks 36>;
|
||||
clocks = <&clks 105>, <&clks 52>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <26>;
|
||||
};
|
||||
|
||||
@ -127,24 +127,12 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_usbh1_vbus: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1reg>;
|
||||
reg = <0>;
|
||||
regulator-name = "usbh1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usbotg_vbus: regulator@1 {
|
||||
reg_hub_reset: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotgreg>;
|
||||
reg = <1>;
|
||||
regulator-name = "usbotg_vbus";
|
||||
reg = <0>;
|
||||
regulator-name = "hub_reset";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
@ -176,6 +164,7 @@
|
||||
reg = <0>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
clock-names = "main_clk";
|
||||
reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -419,7 +408,7 @@
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1>;
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
vbus-supply = <®_hub_reset>;
|
||||
fsl,usbphy = <&usbh1phy>;
|
||||
phy_type = "ulpi";
|
||||
status = "okay";
|
||||
@ -429,7 +418,6 @@
|
||||
dr_mode = "otg";
|
||||
disable-over-current;
|
||||
phy_type = "utmi_wide";
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -335,8 +335,8 @@
|
||||
vpu: vpu@02040000 {
|
||||
compatible = "cnm,coda960";
|
||||
reg = <0x02040000 0x3c000>;
|
||||
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "bit", "jpeg";
|
||||
clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
|
||||
<&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
|
||||
|
||||
@ -159,13 +159,28 @@
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
phy-supply = <®_enet_3v3>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <ðphy1>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
ethphy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet2>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <ðphy2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -142,6 +142,7 @@
|
||||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1021a-scfg", "syscon";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
|
||||
@ -700,11 +700,9 @@
|
||||
};
|
||||
};
|
||||
|
||||
/* Ethernet is on some early development boards and qemu */
|
||||
ethernet@gpmc {
|
||||
compatible = "smsc,lan91c94";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
|
||||
reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
|
||||
|
||||
@ -155,6 +155,15 @@
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
backlight {
|
||||
bl_en: bl-en {
|
||||
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
@ -173,6 +182,27 @@
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
/*
|
||||
* Default drive strength isn't enough to achieve even
|
||||
* high-speed mode on EVB board so bump up to 8ma.
|
||||
*/
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
|
||||
@ -176,7 +176,7 @@
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"IN2L", "Line In Jack",
|
||||
"IN2R", "Line In Jack",
|
||||
"MICBIAS", "IN1L",
|
||||
"Mic", "MICBIAS",
|
||||
"IN1L", "Mic";
|
||||
|
||||
atmel,ssc-controller = <&ssc0>;
|
||||
|
||||
@ -1008,7 +1008,7 @@
|
||||
|
||||
pit: timer@fc068630 {
|
||||
compatible = "atmel,at91sam9260-pit";
|
||||
reg = <0xfc068630 0xf>;
|
||||
reg = <0xfc068630 0x10>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
clocks = <&h32ck>;
|
||||
};
|
||||
|
||||
@ -25,11 +25,11 @@
|
||||
stmpe2401_1 {
|
||||
stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
|
||||
nhk_cfg1 {
|
||||
ste,pins = "GPIO76_B20"; // IRQ line
|
||||
pins = "GPIO76_B20"; // IRQ line
|
||||
ste,input = <0>;
|
||||
};
|
||||
nhk_cfg2 {
|
||||
ste,pins = "GPIO77_B8"; // reset line
|
||||
pins = "GPIO77_B8"; // reset line
|
||||
ste,output = <1>;
|
||||
};
|
||||
};
|
||||
@ -37,11 +37,11 @@
|
||||
stmpe2401_2 {
|
||||
stmpe2401_2_nhk_mode: stmpe2401_2_nhk {
|
||||
nhk_cfg1 {
|
||||
ste,pins = "GPIO78_A8"; // IRQ line
|
||||
pins = "GPIO78_A8"; // IRQ line
|
||||
ste,input = <0>;
|
||||
};
|
||||
nhk_cfg2 {
|
||||
ste,pins = "GPIO79_C9"; // reset line
|
||||
pins = "GPIO79_C9"; // reset line
|
||||
ste,output = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -17,14 +17,6 @@
|
||||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
serial6 = &uart6;
|
||||
serial7 = &uart7;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@ -39,6 +31,14 @@
|
||||
<&ahb_gates 44>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
framebuffer@1 {
|
||||
compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
|
||||
allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
|
||||
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
|
||||
<&ahb_gates 44>, <&ahb_gates 46>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
@ -438,8 +438,8 @@
|
||||
reg-names = "phy_ctrl", "pmu1", "pmu2";
|
||||
clocks = <&usb_clk 8>;
|
||||
clock-names = "usb_phy";
|
||||
resets = <&usb_clk 1>, <&usb_clk 2>;
|
||||
reset-names = "usb1_reset", "usb2_reset";
|
||||
resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
|
||||
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -55,6 +55,12 @@
|
||||
model = "Olimex A10s-Olinuxino Micro";
|
||||
compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
emac: ethernet@01c0b000 {
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -18,10 +18,6 @@
|
||||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@ -390,8 +386,8 @@
|
||||
reg-names = "phy_ctrl", "pmu1";
|
||||
clocks = <&usb_clk 8>;
|
||||
clock-names = "usb_phy";
|
||||
resets = <&usb_clk 1>;
|
||||
reset-names = "usb1_reset";
|
||||
resets = <&usb_clk 0>, <&usb_clk 1>;
|
||||
reset-names = "usb0_reset", "usb1_reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -53,6 +53,10 @@
|
||||
model = "HSG H702";
|
||||
compatible = "hsg,h702", "allwinner,sun5i-a13";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
mmc0: mmc@01c0f000 {
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -54,6 +54,10 @@
|
||||
model = "Olimex A13-Olinuxino Micro";
|
||||
compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
mmc0: mmc@01c0f000 {
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -55,6 +55,10 @@
|
||||
model = "Olimex A13-Olinuxino";
|
||||
compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
mmc0: mmc@01c0f000 {
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -16,11 +16,6 @@
|
||||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -349,8 +344,8 @@
|
||||
reg-names = "phy_ctrl", "pmu1";
|
||||
clocks = <&usb_clk 8>;
|
||||
clock-names = "usb_phy";
|
||||
resets = <&usb_clk 1>;
|
||||
reset-names = "usb1_reset";
|
||||
resets = <&usb_clk 0>, <&usb_clk 1>;
|
||||
reset-names = "usb0_reset", "usb1_reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -53,12 +53,6 @@
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
ethernet0 = &gmac;
|
||||
};
|
||||
|
||||
|
||||
@ -55,6 +55,12 @@
|
||||
model = "LeMaker Banana Pi";
|
||||
compatible = "lemaker,bananapi", "allwinner,sun7i-a20";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart3;
|
||||
serial2 = &uart7;
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
spi0: spi@01c05000 {
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -19,6 +19,14 @@
|
||||
model = "Merrii A20 Hummingbird";
|
||||
compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
mmc0: mmc@01c0f000 {
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -20,6 +20,9 @@
|
||||
compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart6;
|
||||
serial2 = &uart7;
|
||||
spi0 = &spi1;
|
||||
spi1 = &spi2;
|
||||
};
|
||||
|
||||
@ -54,14 +54,6 @@
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
serial6 = &uart6;
|
||||
serial7 = &uart7;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
||||
@ -55,6 +55,10 @@
|
||||
model = "Ippo Q8H Dual Core Tablet (v5)";
|
||||
compatible = "ippo,q8h-v5", "allwinner,sun8i-a23";
|
||||
|
||||
aliases {
|
||||
serial0 = &r_uart;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlyprintk console=ttyS0,115200";
|
||||
};
|
||||
|
||||
@ -52,15 +52,6 @@
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &r_uart;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -54,6 +54,11 @@
|
||||
model = "Merrii A80 Optimus Board";
|
||||
compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart4;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlyprintk console=ttyS0,115200";
|
||||
};
|
||||
|
||||
@ -52,16 +52,6 @@
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
serial6 = &r_uart;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -406,7 +406,7 @@
|
||||
clock-frequency = <400000>;
|
||||
|
||||
magnetometer@c {
|
||||
compatible = "ak,ak8975";
|
||||
compatible = "asahi-kasei,ak8975";
|
||||
reg = <0xc>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -129,13 +129,28 @@
|
||||
|
||||
&fec0 {
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec0>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
status = "okay";
|
||||
|
||||
@ -84,7 +84,8 @@ CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_BATTERY_SBS=y
|
||||
CONFIG_CHARGER_TPS65090=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LM90=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_EXYNOS_THERMAL=y
|
||||
CONFIG_EXYNOS_THERMAL_CORE=y
|
||||
@ -109,11 +110,26 @@ CONFIG_REGULATOR_S2MPA01=y
|
||||
CONFIG_REGULATOR_S2MPS11=y
|
||||
CONFIG_REGULATOR_S5M8767=y
|
||||
CONFIG_REGULATOR_TPS65090=y
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_BRIDGE=y
|
||||
CONFIG_DRM_PTN3460=y
|
||||
CONFIG_DRM_PS8622=y
|
||||
CONFIG_DRM_EXYNOS=y
|
||||
CONFIG_DRM_EXYNOS_FIMD=y
|
||||
CONFIG_DRM_EXYNOS_DP=y
|
||||
CONFIG_DRM_PANEL=y
|
||||
CONFIG_DRM_PANEL_SIMPLE=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_EXYNOS_VIDEO=y
|
||||
CONFIG_EXYNOS_MIPI_DSI=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
CONFIG_LCD_PLATFORM=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_GENERIC=y
|
||||
CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FONTS=y
|
||||
CONFIG_FONT_7x14=y
|
||||
|
||||
@ -68,7 +68,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_GENERIC_CPUFREQ_CPU0=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
|
||||
@ -38,6 +38,16 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
|
||||
vcpu->arch.hcr = HCR_GUEST_MASK;
|
||||
}
|
||||
|
||||
static inline unsigned long vcpu_get_hcr(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return vcpu->arch.hcr;
|
||||
}
|
||||
|
||||
static inline void vcpu_set_hcr(struct kvm_vcpu *vcpu, unsigned long hcr)
|
||||
{
|
||||
vcpu->arch.hcr = hcr;
|
||||
}
|
||||
|
||||
static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return 1;
|
||||
|
||||
@ -125,9 +125,6 @@ struct kvm_vcpu_arch {
|
||||
* Anything that is not used directly from assembly code goes
|
||||
* here.
|
||||
*/
|
||||
/* dcache set/way operation pending */
|
||||
int last_pcpu;
|
||||
cpumask_t require_dcache_flush;
|
||||
|
||||
/* Don't run the guest on this vcpu */
|
||||
bool pause;
|
||||
|
||||
@ -44,6 +44,7 @@
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/highmem.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/pgalloc.h>
|
||||
|
||||
@ -161,13 +162,10 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
|
||||
return (vcpu->arch.cp15[c1_SCTLR] & 0b101) == 0b101;
|
||||
}
|
||||
|
||||
static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
|
||||
unsigned long size,
|
||||
bool ipa_uncached)
|
||||
static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, pfn_t pfn,
|
||||
unsigned long size,
|
||||
bool ipa_uncached)
|
||||
{
|
||||
if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached)
|
||||
kvm_flush_dcache_to_poc((void *)hva, size);
|
||||
|
||||
/*
|
||||
* If we are going to insert an instruction page and the icache is
|
||||
* either VIPT or PIPT, there is a potential problem where the host
|
||||
@ -179,18 +177,77 @@ static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
|
||||
*
|
||||
* VIVT caches are tagged using both the ASID and the VMID and doesn't
|
||||
* need any kind of flushing (DDI 0406C.b - Page B3-1392).
|
||||
*
|
||||
* We need to do this through a kernel mapping (using the
|
||||
* user-space mapping has proved to be the wrong
|
||||
* solution). For that, we need to kmap one page at a time,
|
||||
* and iterate over the range.
|
||||
*/
|
||||
if (icache_is_pipt()) {
|
||||
__cpuc_coherent_user_range(hva, hva + size);
|
||||
} else if (!icache_is_vivt_asid_tagged()) {
|
||||
|
||||
bool need_flush = !vcpu_has_cache_enabled(vcpu) || ipa_uncached;
|
||||
|
||||
VM_BUG_ON(size & PAGE_MASK);
|
||||
|
||||
if (!need_flush && !icache_is_pipt())
|
||||
goto vipt_cache;
|
||||
|
||||
while (size) {
|
||||
void *va = kmap_atomic_pfn(pfn);
|
||||
|
||||
if (need_flush)
|
||||
kvm_flush_dcache_to_poc(va, PAGE_SIZE);
|
||||
|
||||
if (icache_is_pipt())
|
||||
__cpuc_coherent_user_range((unsigned long)va,
|
||||
(unsigned long)va + PAGE_SIZE);
|
||||
|
||||
size -= PAGE_SIZE;
|
||||
pfn++;
|
||||
|
||||
kunmap_atomic(va);
|
||||
}
|
||||
|
||||
vipt_cache:
|
||||
if (!icache_is_pipt() && !icache_is_vivt_asid_tagged()) {
|
||||
/* any kind of VIPT cache */
|
||||
__flush_icache_all();
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __kvm_flush_dcache_pte(pte_t pte)
|
||||
{
|
||||
void *va = kmap_atomic(pte_page(pte));
|
||||
|
||||
kvm_flush_dcache_to_poc(va, PAGE_SIZE);
|
||||
|
||||
kunmap_atomic(va);
|
||||
}
|
||||
|
||||
static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
|
||||
{
|
||||
unsigned long size = PMD_SIZE;
|
||||
pfn_t pfn = pmd_pfn(pmd);
|
||||
|
||||
while (size) {
|
||||
void *va = kmap_atomic_pfn(pfn);
|
||||
|
||||
kvm_flush_dcache_to_poc(va, PAGE_SIZE);
|
||||
|
||||
pfn++;
|
||||
size -= PAGE_SIZE;
|
||||
|
||||
kunmap_atomic(va);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __kvm_flush_dcache_pud(pud_t pud)
|
||||
{
|
||||
}
|
||||
|
||||
#define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x))
|
||||
|
||||
void stage2_flush_vm(struct kvm *kvm);
|
||||
void kvm_set_way_flush(struct kvm_vcpu *vcpu);
|
||||
void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
|
||||
@ -253,21 +253,22 @@
|
||||
.endm
|
||||
|
||||
.macro restore_user_regs, fast = 0, offset = 0
|
||||
ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
|
||||
ldr lr, [sp, #\offset + S_PC]! @ get pc
|
||||
mov r2, sp
|
||||
ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr
|
||||
ldr lr, [r2, #\offset + S_PC]! @ get pc
|
||||
msr spsr_cxsf, r1 @ save in spsr_svc
|
||||
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
|
||||
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
||||
strex r1, r2, [sp] @ clear the exclusive monitor
|
||||
strex r1, r2, [r2] @ clear the exclusive monitor
|
||||
#endif
|
||||
.if \fast
|
||||
ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
|
||||
ldmdb r2, {r1 - lr}^ @ get calling r1 - lr
|
||||
.else
|
||||
ldmdb sp, {r0 - lr}^ @ get calling r0 - lr
|
||||
ldmdb r2, {r0 - lr}^ @ get calling r0 - lr
|
||||
.endif
|
||||
mov r0, r0 @ ARMv5T and earlier require a nop
|
||||
@ after ldm {}^
|
||||
add sp, sp, #S_FRAME_SIZE - S_PC
|
||||
add sp, sp, #\offset + S_FRAME_SIZE
|
||||
movs pc, lr @ return & move spsr_svc into cpsr
|
||||
.endm
|
||||
|
||||
|
||||
@ -116,8 +116,14 @@ int armpmu_event_set_period(struct perf_event *event)
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
if (left > (s64)armpmu->max_period)
|
||||
left = armpmu->max_period;
|
||||
/*
|
||||
* Limit the maximum period to prevent the counter value
|
||||
* from overtaking the one we are about to program. In
|
||||
* effect we are reducing max_period to account for
|
||||
* interrupt latency (and we are being very conservative).
|
||||
*/
|
||||
if (left > (armpmu->max_period >> 1))
|
||||
left = armpmu->max_period >> 1;
|
||||
|
||||
local64_set(&hwc->prev_count, (u64)-left);
|
||||
|
||||
|
||||
@ -657,10 +657,13 @@ int __init arm_add_memory(u64 start, u64 size)
|
||||
|
||||
/*
|
||||
* Ensure that start/size are aligned to a page boundary.
|
||||
* Size is appropriately rounded down, start is rounded up.
|
||||
* Size is rounded down, start is rounded up.
|
||||
*/
|
||||
size -= start & ~PAGE_MASK;
|
||||
aligned_start = PAGE_ALIGN(start);
|
||||
if (aligned_start > start + size)
|
||||
size = 0;
|
||||
else
|
||||
size -= aligned_start - start;
|
||||
|
||||
#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
|
||||
if (aligned_start > ULONG_MAX) {
|
||||
|
||||
@ -281,15 +281,6 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
||||
vcpu->cpu = cpu;
|
||||
vcpu->arch.host_cpu_context = this_cpu_ptr(kvm_host_cpu_state);
|
||||
|
||||
/*
|
||||
* Check whether this vcpu requires the cache to be flushed on
|
||||
* this physical CPU. This is a consequence of doing dcache
|
||||
* operations by set/way on this vcpu. We do it here to be in
|
||||
* a non-preemptible section.
|
||||
*/
|
||||
if (cpumask_test_and_clear_cpu(cpu, &vcpu->arch.require_dcache_flush))
|
||||
flush_cache_all(); /* We'd really want v7_flush_dcache_all() */
|
||||
|
||||
kvm_arm_set_running_vcpu(vcpu);
|
||||
}
|
||||
|
||||
@ -541,7 +532,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
|
||||
ret = kvm_call_hyp(__kvm_vcpu_run, vcpu);
|
||||
|
||||
vcpu->mode = OUTSIDE_GUEST_MODE;
|
||||
vcpu->arch.last_pcpu = smp_processor_id();
|
||||
kvm_guest_exit();
|
||||
trace_kvm_exit(*vcpu_pc(vcpu));
|
||||
/*
|
||||
|
||||
@ -189,82 +189,40 @@ static bool access_l2ectlr(struct kvm_vcpu *vcpu,
|
||||
return true;
|
||||
}
|
||||
|
||||
/* See note at ARM ARM B1.14.4 */
|
||||
/*
|
||||
* See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
|
||||
*/
|
||||
static bool access_dcsw(struct kvm_vcpu *vcpu,
|
||||
const struct coproc_params *p,
|
||||
const struct coproc_reg *r)
|
||||
{
|
||||
unsigned long val;
|
||||
int cpu;
|
||||
|
||||
if (!p->is_write)
|
||||
return read_from_write_only(vcpu, p);
|
||||
|
||||
cpu = get_cpu();
|
||||
|
||||
cpumask_setall(&vcpu->arch.require_dcache_flush);
|
||||
cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
|
||||
|
||||
/* If we were already preempted, take the long way around */
|
||||
if (cpu != vcpu->arch.last_pcpu) {
|
||||
flush_cache_all();
|
||||
goto done;
|
||||
}
|
||||
|
||||
val = *vcpu_reg(vcpu, p->Rt1);
|
||||
|
||||
switch (p->CRm) {
|
||||
case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
|
||||
case 14: /* DCCISW */
|
||||
asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
|
||||
break;
|
||||
|
||||
case 10: /* DCCSW */
|
||||
asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
|
||||
break;
|
||||
}
|
||||
|
||||
done:
|
||||
put_cpu();
|
||||
|
||||
kvm_set_way_flush(vcpu);
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Generic accessor for VM registers. Only called as long as HCR_TVM
|
||||
* is set.
|
||||
* is set. If the guest enables the MMU, we stop trapping the VM
|
||||
* sys_regs and leave it in complete control of the caches.
|
||||
*
|
||||
* Used by the cpu-specific code.
|
||||
*/
|
||||
static bool access_vm_reg(struct kvm_vcpu *vcpu,
|
||||
const struct coproc_params *p,
|
||||
const struct coproc_reg *r)
|
||||
bool access_vm_reg(struct kvm_vcpu *vcpu,
|
||||
const struct coproc_params *p,
|
||||
const struct coproc_reg *r)
|
||||
{
|
||||
bool was_enabled = vcpu_has_cache_enabled(vcpu);
|
||||
|
||||
BUG_ON(!p->is_write);
|
||||
|
||||
vcpu->arch.cp15[r->reg] = *vcpu_reg(vcpu, p->Rt1);
|
||||
if (p->is_64bit)
|
||||
vcpu->arch.cp15[r->reg + 1] = *vcpu_reg(vcpu, p->Rt2);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* SCTLR accessor. Only called as long as HCR_TVM is set. If the
|
||||
* guest enables the MMU, we stop trapping the VM sys_regs and leave
|
||||
* it in complete control of the caches.
|
||||
*
|
||||
* Used by the cpu-specific code.
|
||||
*/
|
||||
bool access_sctlr(struct kvm_vcpu *vcpu,
|
||||
const struct coproc_params *p,
|
||||
const struct coproc_reg *r)
|
||||
{
|
||||
access_vm_reg(vcpu, p, r);
|
||||
|
||||
if (vcpu_has_cache_enabled(vcpu)) { /* MMU+Caches enabled? */
|
||||
vcpu->arch.hcr &= ~HCR_TVM;
|
||||
stage2_flush_vm(vcpu->kvm);
|
||||
}
|
||||
|
||||
kvm_toggle_cache(vcpu, was_enabled);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@ -153,8 +153,8 @@ static inline int cmp_reg(const struct coproc_reg *i1,
|
||||
#define is64 .is_64 = true
|
||||
#define is32 .is_64 = false
|
||||
|
||||
bool access_sctlr(struct kvm_vcpu *vcpu,
|
||||
const struct coproc_params *p,
|
||||
const struct coproc_reg *r);
|
||||
bool access_vm_reg(struct kvm_vcpu *vcpu,
|
||||
const struct coproc_params *p,
|
||||
const struct coproc_reg *r);
|
||||
|
||||
#endif /* __ARM_KVM_COPROC_LOCAL_H__ */
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
static const struct coproc_reg a15_regs[] = {
|
||||
/* SCTLR: swapped by interrupt.S. */
|
||||
{ CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
|
||||
access_sctlr, reset_val, c1_SCTLR, 0x00C50078 },
|
||||
access_vm_reg, reset_val, c1_SCTLR, 0x00C50078 },
|
||||
};
|
||||
|
||||
static struct kvm_coproc_target_table a15_target_table = {
|
||||
|
||||
@ -37,7 +37,7 @@
|
||||
static const struct coproc_reg a7_regs[] = {
|
||||
/* SCTLR: swapped by interrupt.S. */
|
||||
{ CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
|
||||
access_sctlr, reset_val, c1_SCTLR, 0x00C50878 },
|
||||
access_vm_reg, reset_val, c1_SCTLR, 0x00C50878 },
|
||||
};
|
||||
|
||||
static struct kvm_coproc_target_table a7_target_table = {
|
||||
|
||||
@ -58,6 +58,26 @@ static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
|
||||
kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
|
||||
}
|
||||
|
||||
/*
|
||||
* D-Cache management functions. They take the page table entries by
|
||||
* value, as they are flushing the cache using the kernel mapping (or
|
||||
* kmap on 32bit).
|
||||
*/
|
||||
static void kvm_flush_dcache_pte(pte_t pte)
|
||||
{
|
||||
__kvm_flush_dcache_pte(pte);
|
||||
}
|
||||
|
||||
static void kvm_flush_dcache_pmd(pmd_t pmd)
|
||||
{
|
||||
__kvm_flush_dcache_pmd(pmd);
|
||||
}
|
||||
|
||||
static void kvm_flush_dcache_pud(pud_t pud)
|
||||
{
|
||||
__kvm_flush_dcache_pud(pud);
|
||||
}
|
||||
|
||||
static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
|
||||
int min, int max)
|
||||
{
|
||||
@ -119,6 +139,26 @@ static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr)
|
||||
put_page(virt_to_page(pmd));
|
||||
}
|
||||
|
||||
/*
|
||||
* Unmapping vs dcache management:
|
||||
*
|
||||
* If a guest maps certain memory pages as uncached, all writes will
|
||||
* bypass the data cache and go directly to RAM. However, the CPUs
|
||||
* can still speculate reads (not writes) and fill cache lines with
|
||||
* data.
|
||||
*
|
||||
* Those cache lines will be *clean* cache lines though, so a
|
||||
* clean+invalidate operation is equivalent to an invalidate
|
||||
* operation, because no cache lines are marked dirty.
|
||||
*
|
||||
* Those clean cache lines could be filled prior to an uncached write
|
||||
* by the guest, and the cache coherent IO subsystem would therefore
|
||||
* end up writing old data to disk.
|
||||
*
|
||||
* This is why right after unmapping a page/section and invalidating
|
||||
* the corresponding TLBs, we call kvm_flush_dcache_p*() to make sure
|
||||
* the IO subsystem will never hit in the cache.
|
||||
*/
|
||||
static void unmap_ptes(struct kvm *kvm, pmd_t *pmd,
|
||||
phys_addr_t addr, phys_addr_t end)
|
||||
{
|
||||
@ -128,9 +168,16 @@ static void unmap_ptes(struct kvm *kvm, pmd_t *pmd,
|
||||
start_pte = pte = pte_offset_kernel(pmd, addr);
|
||||
do {
|
||||
if (!pte_none(*pte)) {
|
||||
pte_t old_pte = *pte;
|
||||
|
||||
kvm_set_pte(pte, __pte(0));
|
||||
put_page(virt_to_page(pte));
|
||||
kvm_tlb_flush_vmid_ipa(kvm, addr);
|
||||
|
||||
/* No need to invalidate the cache for device mappings */
|
||||
if ((pte_val(old_pte) & PAGE_S2_DEVICE) != PAGE_S2_DEVICE)
|
||||
kvm_flush_dcache_pte(old_pte);
|
||||
|
||||
put_page(virt_to_page(pte));
|
||||
}
|
||||
} while (pte++, addr += PAGE_SIZE, addr != end);
|
||||
|
||||
@ -149,8 +196,13 @@ static void unmap_pmds(struct kvm *kvm, pud_t *pud,
|
||||
next = kvm_pmd_addr_end(addr, end);
|
||||
if (!pmd_none(*pmd)) {
|
||||
if (kvm_pmd_huge(*pmd)) {
|
||||
pmd_t old_pmd = *pmd;
|
||||
|
||||
pmd_clear(pmd);
|
||||
kvm_tlb_flush_vmid_ipa(kvm, addr);
|
||||
|
||||
kvm_flush_dcache_pmd(old_pmd);
|
||||
|
||||
put_page(virt_to_page(pmd));
|
||||
} else {
|
||||
unmap_ptes(kvm, pmd, addr, next);
|
||||
@ -173,8 +225,13 @@ static void unmap_puds(struct kvm *kvm, pgd_t *pgd,
|
||||
next = kvm_pud_addr_end(addr, end);
|
||||
if (!pud_none(*pud)) {
|
||||
if (pud_huge(*pud)) {
|
||||
pud_t old_pud = *pud;
|
||||
|
||||
pud_clear(pud);
|
||||
kvm_tlb_flush_vmid_ipa(kvm, addr);
|
||||
|
||||
kvm_flush_dcache_pud(old_pud);
|
||||
|
||||
put_page(virt_to_page(pud));
|
||||
} else {
|
||||
unmap_pmds(kvm, pud, addr, next);
|
||||
@ -209,10 +266,9 @@ static void stage2_flush_ptes(struct kvm *kvm, pmd_t *pmd,
|
||||
|
||||
pte = pte_offset_kernel(pmd, addr);
|
||||
do {
|
||||
if (!pte_none(*pte)) {
|
||||
hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);
|
||||
kvm_flush_dcache_to_poc((void*)hva, PAGE_SIZE);
|
||||
}
|
||||
if (!pte_none(*pte) &&
|
||||
(pte_val(*pte) & PAGE_S2_DEVICE) != PAGE_S2_DEVICE)
|
||||
kvm_flush_dcache_pte(*pte);
|
||||
} while (pte++, addr += PAGE_SIZE, addr != end);
|
||||
}
|
||||
|
||||
@ -226,12 +282,10 @@ static void stage2_flush_pmds(struct kvm *kvm, pud_t *pud,
|
||||
do {
|
||||
next = kvm_pmd_addr_end(addr, end);
|
||||
if (!pmd_none(*pmd)) {
|
||||
if (kvm_pmd_huge(*pmd)) {
|
||||
hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);
|
||||
kvm_flush_dcache_to_poc((void*)hva, PMD_SIZE);
|
||||
} else {
|
||||
if (kvm_pmd_huge(*pmd))
|
||||
kvm_flush_dcache_pmd(*pmd);
|
||||
else
|
||||
stage2_flush_ptes(kvm, pmd, addr, next);
|
||||
}
|
||||
}
|
||||
} while (pmd++, addr = next, addr != end);
|
||||
}
|
||||
@ -246,12 +300,10 @@ static void stage2_flush_puds(struct kvm *kvm, pgd_t *pgd,
|
||||
do {
|
||||
next = kvm_pud_addr_end(addr, end);
|
||||
if (!pud_none(*pud)) {
|
||||
if (pud_huge(*pud)) {
|
||||
hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);
|
||||
kvm_flush_dcache_to_poc((void*)hva, PUD_SIZE);
|
||||
} else {
|
||||
if (pud_huge(*pud))
|
||||
kvm_flush_dcache_pud(*pud);
|
||||
else
|
||||
stage2_flush_pmds(kvm, pud, addr, next);
|
||||
}
|
||||
}
|
||||
} while (pud++, addr = next, addr != end);
|
||||
}
|
||||
@ -278,7 +330,7 @@ static void stage2_flush_memslot(struct kvm *kvm,
|
||||
* Go through the stage 2 page tables and invalidate any cache lines
|
||||
* backing memory already mapped to the VM.
|
||||
*/
|
||||
void stage2_flush_vm(struct kvm *kvm)
|
||||
static void stage2_flush_vm(struct kvm *kvm)
|
||||
{
|
||||
struct kvm_memslots *slots;
|
||||
struct kvm_memory_slot *memslot;
|
||||
@ -905,6 +957,12 @@ static bool kvm_is_device_pfn(unsigned long pfn)
|
||||
return !pfn_valid(pfn);
|
||||
}
|
||||
|
||||
static void coherent_cache_guest_page(struct kvm_vcpu *vcpu, pfn_t pfn,
|
||||
unsigned long size, bool uncached)
|
||||
{
|
||||
__coherent_cache_guest_page(vcpu, pfn, size, uncached);
|
||||
}
|
||||
|
||||
static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
|
||||
struct kvm_memory_slot *memslot, unsigned long hva,
|
||||
unsigned long fault_status)
|
||||
@ -994,8 +1052,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
|
||||
kvm_set_s2pmd_writable(&new_pmd);
|
||||
kvm_set_pfn_dirty(pfn);
|
||||
}
|
||||
coherent_cache_guest_page(vcpu, hva & PMD_MASK, PMD_SIZE,
|
||||
fault_ipa_uncached);
|
||||
coherent_cache_guest_page(vcpu, pfn, PMD_SIZE, fault_ipa_uncached);
|
||||
ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd);
|
||||
} else {
|
||||
pte_t new_pte = pfn_pte(pfn, mem_type);
|
||||
@ -1003,8 +1060,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
|
||||
kvm_set_s2pte_writable(&new_pte);
|
||||
kvm_set_pfn_dirty(pfn);
|
||||
}
|
||||
coherent_cache_guest_page(vcpu, hva, PAGE_SIZE,
|
||||
fault_ipa_uncached);
|
||||
coherent_cache_guest_page(vcpu, pfn, PAGE_SIZE, fault_ipa_uncached);
|
||||
ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte,
|
||||
pgprot_val(mem_type) == pgprot_val(PAGE_S2_DEVICE));
|
||||
}
|
||||
@ -1411,3 +1467,71 @@ void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
|
||||
unmap_stage2_range(kvm, gpa, size);
|
||||
spin_unlock(&kvm->mmu_lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
|
||||
*
|
||||
* Main problems:
|
||||
* - S/W ops are local to a CPU (not broadcast)
|
||||
* - We have line migration behind our back (speculation)
|
||||
* - System caches don't support S/W at all (damn!)
|
||||
*
|
||||
* In the face of the above, the best we can do is to try and convert
|
||||
* S/W ops to VA ops. Because the guest is not allowed to infer the
|
||||
* S/W to PA mapping, it can only use S/W to nuke the whole cache,
|
||||
* which is a rather good thing for us.
|
||||
*
|
||||
* Also, it is only used when turning caches on/off ("The expected
|
||||
* usage of the cache maintenance instructions that operate by set/way
|
||||
* is associated with the cache maintenance instructions associated
|
||||
* with the powerdown and powerup of caches, if this is required by
|
||||
* the implementation.").
|
||||
*
|
||||
* We use the following policy:
|
||||
*
|
||||
* - If we trap a S/W operation, we enable VM trapping to detect
|
||||
* caches being turned on/off, and do a full clean.
|
||||
*
|
||||
* - We flush the caches on both caches being turned on and off.
|
||||
*
|
||||
* - Once the caches are enabled, we stop trapping VM ops.
|
||||
*/
|
||||
void kvm_set_way_flush(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
unsigned long hcr = vcpu_get_hcr(vcpu);
|
||||
|
||||
/*
|
||||
* If this is the first time we do a S/W operation
|
||||
* (i.e. HCR_TVM not set) flush the whole memory, and set the
|
||||
* VM trapping.
|
||||
*
|
||||
* Otherwise, rely on the VM trapping to wait for the MMU +
|
||||
* Caches to be turned off. At that point, we'll be able to
|
||||
* clean the caches again.
|
||||
*/
|
||||
if (!(hcr & HCR_TVM)) {
|
||||
trace_kvm_set_way_flush(*vcpu_pc(vcpu),
|
||||
vcpu_has_cache_enabled(vcpu));
|
||||
stage2_flush_vm(vcpu->kvm);
|
||||
vcpu_set_hcr(vcpu, hcr | HCR_TVM);
|
||||
}
|
||||
}
|
||||
|
||||
void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled)
|
||||
{
|
||||
bool now_enabled = vcpu_has_cache_enabled(vcpu);
|
||||
|
||||
/*
|
||||
* If switching the MMU+caches on, need to invalidate the caches.
|
||||
* If switching it off, need to clean the caches.
|
||||
* Clean + invalidate does the trick always.
|
||||
*/
|
||||
if (now_enabled != was_enabled)
|
||||
stage2_flush_vm(vcpu->kvm);
|
||||
|
||||
/* Caches are now on, stop trapping VM ops (until a S/W op) */
|
||||
if (now_enabled)
|
||||
vcpu_set_hcr(vcpu, vcpu_get_hcr(vcpu) & ~HCR_TVM);
|
||||
|
||||
trace_kvm_toggle_cache(*vcpu_pc(vcpu), was_enabled, now_enabled);
|
||||
}
|
||||
|
||||
@ -223,6 +223,45 @@ TRACE_EVENT(kvm_hvc,
|
||||
__entry->vcpu_pc, __entry->r0, __entry->imm)
|
||||
);
|
||||
|
||||
TRACE_EVENT(kvm_set_way_flush,
|
||||
TP_PROTO(unsigned long vcpu_pc, bool cache),
|
||||
TP_ARGS(vcpu_pc, cache),
|
||||
|
||||
TP_STRUCT__entry(
|
||||
__field( unsigned long, vcpu_pc )
|
||||
__field( bool, cache )
|
||||
),
|
||||
|
||||
TP_fast_assign(
|
||||
__entry->vcpu_pc = vcpu_pc;
|
||||
__entry->cache = cache;
|
||||
),
|
||||
|
||||
TP_printk("S/W flush at 0x%016lx (cache %s)",
|
||||
__entry->vcpu_pc, __entry->cache ? "on" : "off")
|
||||
);
|
||||
|
||||
TRACE_EVENT(kvm_toggle_cache,
|
||||
TP_PROTO(unsigned long vcpu_pc, bool was, bool now),
|
||||
TP_ARGS(vcpu_pc, was, now),
|
||||
|
||||
TP_STRUCT__entry(
|
||||
__field( unsigned long, vcpu_pc )
|
||||
__field( bool, was )
|
||||
__field( bool, now )
|
||||
),
|
||||
|
||||
TP_fast_assign(
|
||||
__entry->vcpu_pc = vcpu_pc;
|
||||
__entry->was = was;
|
||||
__entry->now = now;
|
||||
),
|
||||
|
||||
TP_printk("VM op at 0x%016lx (cache was %s, now %s)",
|
||||
__entry->vcpu_pc, __entry->was ? "on" : "off",
|
||||
__entry->now ? "on" : "off")
|
||||
);
|
||||
|
||||
#endif /* _TRACE_KVM_H */
|
||||
|
||||
#undef TRACE_INCLUDE_PATH
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
@ -26,8 +27,25 @@
|
||||
|
||||
#include "generic.h"
|
||||
|
||||
static int ksz8081_phy_fixup(struct phy_device *phy)
|
||||
{
|
||||
int value;
|
||||
|
||||
value = phy_read(phy, 0x16);
|
||||
value &= ~0x20;
|
||||
phy_write(phy, 0x16, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init sama5_dt_device_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("atmel,sama5d4ek") &&
|
||||
IS_ENABLED(CONFIG_PHYLIB)) {
|
||||
phy_register_fixup_for_id("fc028000.etherne:00",
|
||||
ksz8081_phy_fixup);
|
||||
}
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
|
||||
@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||
post_div_table[1].div = 1;
|
||||
post_div_table[2].div = 1;
|
||||
video_div_table[1].div = 1;
|
||||
video_div_table[2].div = 1;
|
||||
video_div_table[3].div = 1;
|
||||
}
|
||||
|
||||
clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
|
||||
@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
||||
clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
|
||||
clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
|
||||
|
||||
clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
|
||||
clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
}
|
||||
|
||||
@ -189,6 +189,13 @@ static void __init armada_375_380_coherency_init(struct device_node *np)
|
||||
coherency_cpu_base = of_iomap(np, 0);
|
||||
arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
|
||||
|
||||
/*
|
||||
* We should switch the PL310 to I/O coherency mode only if
|
||||
* I/O coherency is actually enabled.
|
||||
*/
|
||||
if (!coherency_available())
|
||||
return;
|
||||
|
||||
/*
|
||||
* Add the PL310 property "arm,io-coherent". This makes sure the
|
||||
* outer sync operation is not used, which allows to
|
||||
@ -246,9 +253,14 @@ static int coherency_type(void)
|
||||
return type;
|
||||
}
|
||||
|
||||
/*
|
||||
* As a precaution, we currently completely disable hardware I/O
|
||||
* coherency, until enough testing is done with automatic I/O
|
||||
* synchronization barriers to validate that it is a proper solution.
|
||||
*/
|
||||
int coherency_available(void)
|
||||
{
|
||||
return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
|
||||
return false;
|
||||
}
|
||||
|
||||
int __init coherency_init(void)
|
||||
|
||||
@ -77,6 +77,24 @@ MACHINE_END
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
/* Some boards need board name for legacy userspace in /proc/cpuinfo */
|
||||
static const char *const n900_boards_compat[] __initconst = {
|
||||
"nokia,omap3-n900",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3430_init_early,
|
||||
.init_machine = omap_generic_init,
|
||||
.init_late = omap3_init_late,
|
||||
.init_time = omap3_sync32k_timer_init,
|
||||
.dt_compat = n900_boards_compat,
|
||||
.restart = omap3xxx_restart,
|
||||
MACHINE_END
|
||||
|
||||
/* Generic omap3 boards, most boards can use these */
|
||||
static const char *const omap3_boards_compat[] __initconst = {
|
||||
"ti,omap3430",
|
||||
"ti,omap3",
|
||||
|
||||
@ -211,6 +211,7 @@ extern struct device *omap2_get_iva_device(void);
|
||||
extern struct device *omap2_get_l3_device(void);
|
||||
extern struct device *omap4_get_dsp_device(void);
|
||||
|
||||
unsigned int omap4_xlate_irq(unsigned int hwirq);
|
||||
void omap_gic_of_init(void);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
@ -249,6 +250,7 @@ extern void omap4_cpu_die(unsigned int cpu);
|
||||
extern struct smp_operations omap4_smp_ops;
|
||||
|
||||
extern void omap5_secondary_startup(void);
|
||||
extern void omap5_secondary_hyp_startup(void);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(CONFIG_PM)
|
||||
|
||||
@ -286,6 +286,10 @@
|
||||
#define OMAP5XXX_CONTROL_STATUS 0x134
|
||||
#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
|
||||
|
||||
/* DRA7XX CONTROL CORE BOOTSTRAP */
|
||||
#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
|
||||
#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
|
||||
|
||||
/*
|
||||
* REVISIT: This list of registers is not comprehensive - there are more
|
||||
* that should be added.
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
|
||||
/* Physical address needed since MMU not enabled yet on secondary core */
|
||||
#define AUX_CORE_BOOT0_PA 0x48281800
|
||||
#define API_HYP_ENTRY 0x102
|
||||
|
||||
/*
|
||||
* OMAP5 specific entry point for secondary CPU to jump from ROM
|
||||
@ -40,6 +41,26 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
|
||||
bne wait
|
||||
b secondary_startup
|
||||
ENDPROC(omap5_secondary_startup)
|
||||
/*
|
||||
* Same as omap5_secondary_startup except we call into the ROM to
|
||||
* enable HYP mode first. This is called instead of
|
||||
* omap5_secondary_startup if the primary CPU was put into HYP mode by
|
||||
* the boot loader.
|
||||
*/
|
||||
ENTRY(omap5_secondary_hyp_startup)
|
||||
wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
|
||||
ldr r0, [r2]
|
||||
mov r0, r0, lsr #5
|
||||
mrc p15, 0, r4, c0, c0, 5
|
||||
and r4, r4, #0x0f
|
||||
cmp r0, r4
|
||||
bne wait_2
|
||||
ldr r12, =API_HYP_ENTRY
|
||||
adr r0, hyp_boot
|
||||
smc #0
|
||||
hyp_boot:
|
||||
b secondary_startup
|
||||
ENDPROC(omap5_secondary_hyp_startup)
|
||||
/*
|
||||
* OMAP4 specific entry point for secondary CPU to jump from ROM
|
||||
* code. This routine also provides a holding flag into which
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/virt.h>
|
||||
|
||||
#include "omap-secure.h"
|
||||
#include "omap-wakeupgen.h"
|
||||
@ -227,8 +228,16 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
|
||||
if (omap_secure_apis_support())
|
||||
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
|
||||
else
|
||||
writel_relaxed(virt_to_phys(omap5_secondary_startup),
|
||||
base + OMAP_AUX_CORE_BOOT_1);
|
||||
/*
|
||||
* If the boot CPU is in HYP mode then start secondary
|
||||
* CPU in HYP mode as well.
|
||||
*/
|
||||
if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
|
||||
writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
|
||||
base + OMAP_AUX_CORE_BOOT_1);
|
||||
else
|
||||
writel_relaxed(virt_to_phys(omap5_secondary_startup),
|
||||
base + OMAP_AUX_CORE_BOOT_1);
|
||||
|
||||
}
|
||||
|
||||
|
||||
@ -256,6 +256,38 @@ static int __init omap4_sar_ram_init(void)
|
||||
}
|
||||
omap_early_initcall(omap4_sar_ram_init);
|
||||
|
||||
static struct of_device_id gic_match[] = {
|
||||
{ .compatible = "arm,cortex-a9-gic", },
|
||||
{ .compatible = "arm,cortex-a15-gic", },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct device_node *gic_node;
|
||||
|
||||
unsigned int omap4_xlate_irq(unsigned int hwirq)
|
||||
{
|
||||
struct of_phandle_args irq_data;
|
||||
unsigned int irq;
|
||||
|
||||
if (!gic_node)
|
||||
gic_node = of_find_matching_node(NULL, gic_match);
|
||||
|
||||
if (WARN_ON(!gic_node))
|
||||
return hwirq;
|
||||
|
||||
irq_data.np = gic_node;
|
||||
irq_data.args_count = 3;
|
||||
irq_data.args[0] = 0;
|
||||
irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
|
||||
irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
|
||||
|
||||
irq = irq_create_of_mapping(&irq_data);
|
||||
if (WARN_ON(!irq))
|
||||
irq = hwirq;
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
void __init omap_gic_of_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
@ -3534,9 +3534,15 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
|
||||
|
||||
mpu_irqs_cnt = _count_mpu_irqs(oh);
|
||||
for (i = 0; i < mpu_irqs_cnt; i++) {
|
||||
unsigned int irq;
|
||||
|
||||
if (oh->xlate_irq)
|
||||
irq = oh->xlate_irq((oh->mpu_irqs + i)->irq);
|
||||
else
|
||||
irq = (oh->mpu_irqs + i)->irq;
|
||||
(res + r)->name = (oh->mpu_irqs + i)->name;
|
||||
(res + r)->start = (oh->mpu_irqs + i)->irq;
|
||||
(res + r)->end = (oh->mpu_irqs + i)->irq;
|
||||
(res + r)->start = irq;
|
||||
(res + r)->end = irq;
|
||||
(res + r)->flags = IORESOURCE_IRQ;
|
||||
r++;
|
||||
}
|
||||
|
||||
@ -676,6 +676,7 @@ struct omap_hwmod {
|
||||
spinlock_t _lock;
|
||||
struct list_head node;
|
||||
struct omap_hwmod_ocp_if *_mpu_port;
|
||||
unsigned int (*xlate_irq)(unsigned int);
|
||||
u16 flags;
|
||||
u8 mpu_rt_idx;
|
||||
u8 response_lat;
|
||||
|
||||
@ -479,6 +479,7 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
|
||||
.class = &omap44xx_dma_hwmod_class,
|
||||
.clkdm_name = "l3_dma_clkdm",
|
||||
.mpu_irqs = omap44xx_dma_system_irqs,
|
||||
.xlate_irq = omap4_xlate_irq,
|
||||
.main_clk = "l3_div_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
@ -640,6 +641,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
|
||||
.class = &omap44xx_dispc_hwmod_class,
|
||||
.clkdm_name = "l3_dss_clkdm",
|
||||
.mpu_irqs = omap44xx_dss_dispc_irqs,
|
||||
.xlate_irq = omap4_xlate_irq,
|
||||
.sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
|
||||
.main_clk = "dss_dss_clk",
|
||||
.prcm = {
|
||||
@ -693,6 +695,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
|
||||
.class = &omap44xx_dsi_hwmod_class,
|
||||
.clkdm_name = "l3_dss_clkdm",
|
||||
.mpu_irqs = omap44xx_dss_dsi1_irqs,
|
||||
.xlate_irq = omap4_xlate_irq,
|
||||
.sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
|
||||
.main_clk = "dss_dss_clk",
|
||||
.prcm = {
|
||||
@ -726,6 +729,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
|
||||
.class = &omap44xx_dsi_hwmod_class,
|
||||
.clkdm_name = "l3_dss_clkdm",
|
||||
.mpu_irqs = omap44xx_dss_dsi2_irqs,
|
||||
.xlate_irq = omap4_xlate_irq,
|
||||
.sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
|
||||
.main_clk = "dss_dss_clk",
|
||||
.prcm = {
|
||||
@ -784,6 +788,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
|
||||
*/
|
||||
.flags = HWMOD_SWSUP_SIDLE,
|
||||
.mpu_irqs = omap44xx_dss_hdmi_irqs,
|
||||
.xlate_irq = omap4_xlate_irq,
|
||||
.sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
|
||||
.main_clk = "dss_48mhz_clk",
|
||||
.prcm = {
|
||||
|
||||
@ -288,6 +288,7 @@ static struct omap_hwmod omap54xx_dma_system_hwmod = {
|
||||
.class = &omap54xx_dma_hwmod_class,
|
||||
.clkdm_name = "dma_clkdm",
|
||||
.mpu_irqs = omap54xx_dma_system_irqs,
|
||||
.xlate_irq = omap4_xlate_irq,
|
||||
.main_clk = "l3_iclk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
|
||||
@ -498,6 +498,7 @@ struct omap_prcm_irq_setup {
|
||||
u8 nr_irqs;
|
||||
const struct omap_prcm_irq *irqs;
|
||||
int irq;
|
||||
unsigned int (*xlate_irq)(unsigned int);
|
||||
void (*read_pending_irqs)(unsigned long *events);
|
||||
void (*ocp_barrier)(void);
|
||||
void (*save_and_clear_irqen)(u32 *saved_mask);
|
||||
|
||||
@ -49,6 +49,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
|
||||
.irqs = omap4_prcm_irqs,
|
||||
.nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
|
||||
.irq = 11 + OMAP44XX_IRQ_GIC_START,
|
||||
.xlate_irq = omap4_xlate_irq,
|
||||
.read_pending_irqs = &omap44xx_prm_read_pending_irqs,
|
||||
.ocp_barrier = &omap44xx_prm_ocp_barrier,
|
||||
.save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
|
||||
@ -751,8 +752,10 @@ static int omap44xx_prm_late_init(void)
|
||||
}
|
||||
|
||||
/* Once OMAP4 DT is filled as well */
|
||||
if (irq_num >= 0)
|
||||
if (irq_num >= 0) {
|
||||
omap4_prcm_irq_setup.irq = irq_num;
|
||||
omap4_prcm_irq_setup.xlate_irq = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
omap44xx_prm_enable_io_wakeup();
|
||||
|
||||
@ -187,6 +187,7 @@ int omap_prcm_event_to_irq(const char *name)
|
||||
*/
|
||||
void omap_prcm_irq_cleanup(void)
|
||||
{
|
||||
unsigned int irq;
|
||||
int i;
|
||||
|
||||
if (!prcm_irq_setup) {
|
||||
@ -211,7 +212,11 @@ void omap_prcm_irq_cleanup(void)
|
||||
kfree(prcm_irq_setup->priority_mask);
|
||||
prcm_irq_setup->priority_mask = NULL;
|
||||
|
||||
irq_set_chained_handler(prcm_irq_setup->irq, NULL);
|
||||
if (prcm_irq_setup->xlate_irq)
|
||||
irq = prcm_irq_setup->xlate_irq(prcm_irq_setup->irq);
|
||||
else
|
||||
irq = prcm_irq_setup->irq;
|
||||
irq_set_chained_handler(irq, NULL);
|
||||
|
||||
if (prcm_irq_setup->base_irq > 0)
|
||||
irq_free_descs(prcm_irq_setup->base_irq,
|
||||
@ -259,6 +264,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
|
||||
int offset, i;
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_chip_type *ct;
|
||||
unsigned int irq;
|
||||
|
||||
if (!irq_setup)
|
||||
return -EINVAL;
|
||||
@ -298,7 +304,11 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
|
||||
1 << (offset & 0x1f);
|
||||
}
|
||||
|
||||
irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
|
||||
if (irq_setup->xlate_irq)
|
||||
irq = irq_setup->xlate_irq(irq_setup->irq);
|
||||
else
|
||||
irq = irq_setup->irq;
|
||||
irq_set_chained_handler(irq, omap_prcm_irq_handler);
|
||||
|
||||
irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
|
||||
0);
|
||||
|
||||
@ -54,6 +54,7 @@
|
||||
|
||||
#include "soc.h"
|
||||
#include "common.h"
|
||||
#include "control.h"
|
||||
#include "powerdomain.h"
|
||||
#include "omap-secure.h"
|
||||
|
||||
@ -496,7 +497,8 @@ static void __init realtime_counter_init(void)
|
||||
void __iomem *base;
|
||||
static struct clk *sys_clk;
|
||||
unsigned long rate;
|
||||
unsigned int reg, num, den;
|
||||
unsigned int reg;
|
||||
unsigned long long num, den;
|
||||
|
||||
base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
|
||||
if (!base) {
|
||||
@ -511,13 +513,42 @@ static void __init realtime_counter_init(void)
|
||||
}
|
||||
|
||||
rate = clk_get_rate(sys_clk);
|
||||
|
||||
if (soc_is_dra7xx()) {
|
||||
/*
|
||||
* Errata i856 says the 32.768KHz crystal does not start at
|
||||
* power on, so the CPU falls back to an emulated 32KHz clock
|
||||
* based on sysclk / 610 instead. This causes the master counter
|
||||
* frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
|
||||
* (OR sysclk * 75 / 244)
|
||||
*
|
||||
* This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
|
||||
* Of course any board built without a populated 32.768KHz
|
||||
* crystal would also need this fix even if the CPU is fixed
|
||||
* later.
|
||||
*
|
||||
* Either case can be detected by using the two speedselect bits
|
||||
* If they are not 0, then the 32.768KHz clock driving the
|
||||
* coarse counter that corrects the fine counter every time it
|
||||
* ticks is actually rate/610 rather than 32.768KHz and we
|
||||
* should compensate to avoid the 570ppm (at 20MHz, much worse
|
||||
* at other rates) too fast system time.
|
||||
*/
|
||||
reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
|
||||
if (reg & DRA7_SPEEDSELECT_MASK) {
|
||||
num = 75;
|
||||
den = 244;
|
||||
goto sysclk1_based;
|
||||
}
|
||||
}
|
||||
|
||||
/* Numerator/denumerator values refer TRM Realtime Counter section */
|
||||
switch (rate) {
|
||||
case 1200000:
|
||||
case 12000000:
|
||||
num = 64;
|
||||
den = 125;
|
||||
break;
|
||||
case 1300000:
|
||||
case 13000000:
|
||||
num = 768;
|
||||
den = 1625;
|
||||
break;
|
||||
@ -529,11 +560,11 @@ static void __init realtime_counter_init(void)
|
||||
num = 192;
|
||||
den = 625;
|
||||
break;
|
||||
case 2600000:
|
||||
case 26000000:
|
||||
num = 384;
|
||||
den = 1625;
|
||||
break;
|
||||
case 2700000:
|
||||
case 27000000:
|
||||
num = 256;
|
||||
den = 1125;
|
||||
break;
|
||||
@ -545,6 +576,7 @@ static void __init realtime_counter_init(void)
|
||||
break;
|
||||
}
|
||||
|
||||
sysclk1_based:
|
||||
/* Program numerator and denumerator registers */
|
||||
reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
|
||||
NUMERATOR_DENUMERATOR_MASK;
|
||||
@ -556,7 +588,7 @@ static void __init realtime_counter_init(void)
|
||||
reg |= den;
|
||||
writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
|
||||
|
||||
arch_timer_freq = (rate / den) * num;
|
||||
arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
|
||||
set_cntfreq();
|
||||
|
||||
iounmap(base);
|
||||
|
||||
@ -66,19 +66,24 @@ void __init omap_pmic_init(int bus, u32 clkrate,
|
||||
omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP4
|
||||
void __init omap4_pmic_init(const char *pmic_type,
|
||||
struct twl4030_platform_data *pmic_data,
|
||||
struct i2c_board_info *devices, int nr_devices)
|
||||
{
|
||||
/* PMIC part*/
|
||||
unsigned int irq;
|
||||
|
||||
omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
|
||||
omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
|
||||
omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data);
|
||||
irq = omap4_xlate_irq(7 + OMAP44XX_IRQ_GIC_START);
|
||||
omap_pmic_init(1, 400, pmic_type, irq, pmic_data);
|
||||
|
||||
/* Register additional devices on i2c1 bus if needed */
|
||||
if (devices)
|
||||
i2c_register_board_info(1, devices, nr_devices);
|
||||
}
|
||||
#endif
|
||||
|
||||
void __init omap_pmic_late_init(void)
|
||||
{
|
||||
|
||||
@ -19,11 +19,37 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include "core.h"
|
||||
|
||||
#define RK3288_GRF_SOC_CON0 0x244
|
||||
|
||||
static void __init rockchip_timer_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("rockchip,rk3288")) {
|
||||
struct regmap *grf;
|
||||
|
||||
/*
|
||||
* Disable auto jtag/sdmmc switching that causes issues
|
||||
* with the mmc controllers making them unreliable
|
||||
*/
|
||||
grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf");
|
||||
if (!IS_ERR(grf))
|
||||
regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
|
||||
else
|
||||
pr_err("rockchip: could not get grf syscon\n");
|
||||
}
|
||||
|
||||
of_clk_init(NULL);
|
||||
clocksource_of_init();
|
||||
}
|
||||
|
||||
static void __init rockchip_dt_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
@ -42,6 +68,7 @@ static const char * const rockchip_board_dt_compat[] = {
|
||||
DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
|
||||
.l2c_aux_val = 0,
|
||||
.l2c_aux_mask = ~0,
|
||||
.init_time = rockchip_timer_init,
|
||||
.dt_compat = rockchip_board_dt_compat,
|
||||
.init_machine = rockchip_dt_init,
|
||||
MACHINE_END
|
||||
|
||||
@ -18,6 +18,8 @@
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mfd/tmio.h>
|
||||
#include <linux/mmc/host.h>
|
||||
@ -273,6 +275,22 @@ static void __init ape6evm_add_standard_devices(void)
|
||||
sizeof(ape6evm_leds_pdata));
|
||||
}
|
||||
|
||||
static void __init ape6evm_legacy_init_time(void)
|
||||
{
|
||||
/* Do not invoke DT-based timers via clocksource_of_init() */
|
||||
}
|
||||
|
||||
static void __init ape6evm_legacy_init_irq(void)
|
||||
{
|
||||
void __iomem *gic_dist_base = ioremap_nocache(0xf1001000, 0x1000);
|
||||
void __iomem *gic_cpu_base = ioremap_nocache(0xf1002000, 0x1000);
|
||||
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
|
||||
/* Do not invoke DT-based interrupt code via irqchip_init() */
|
||||
}
|
||||
|
||||
|
||||
static const char *ape6evm_boards_compat_dt[] __initdata = {
|
||||
"renesas,ape6evm",
|
||||
NULL,
|
||||
@ -280,7 +298,9 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
|
||||
|
||||
DT_MACHINE_START(APE6EVM_DT, "ape6evm")
|
||||
.init_early = shmobile_init_delay,
|
||||
.init_irq = ape6evm_legacy_init_irq,
|
||||
.init_machine = ape6evm_add_standard_devices,
|
||||
.init_late = shmobile_init_late,
|
||||
.dt_compat = ape6evm_boards_compat_dt,
|
||||
.init_time = ape6evm_legacy_init_time,
|
||||
MACHINE_END
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
#include <linux/input.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/mfd/tmio.h>
|
||||
@ -811,6 +813,16 @@ static void __init lager_init(void)
|
||||
lager_ksz8041_fixup);
|
||||
}
|
||||
|
||||
static void __init lager_legacy_init_irq(void)
|
||||
{
|
||||
void __iomem *gic_dist_base = ioremap_nocache(0xf1001000, 0x1000);
|
||||
void __iomem *gic_cpu_base = ioremap_nocache(0xf1002000, 0x1000);
|
||||
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
|
||||
/* Do not invoke DT-based interrupt code via irqchip_init() */
|
||||
}
|
||||
|
||||
static const char * const lager_boards_compat_dt[] __initconst = {
|
||||
"renesas,lager",
|
||||
NULL,
|
||||
@ -819,6 +831,7 @@ static const char * const lager_boards_compat_dt[] __initconst = {
|
||||
DT_MACHINE_START(LAGER_DT, "lager")
|
||||
.smp = smp_ops(r8a7790_smp_ops),
|
||||
.init_early = shmobile_init_delay,
|
||||
.init_irq = lager_legacy_init_irq,
|
||||
.init_time = rcar_gen2_timer_init,
|
||||
.init_machine = lager_init,
|
||||
.init_late = shmobile_init_late,
|
||||
|
||||
@ -800,7 +800,14 @@ void __init r8a7740_init_irq_of(void)
|
||||
void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
|
||||
void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
|
||||
|
||||
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
||||
void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
|
||||
void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
|
||||
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
#else
|
||||
irqchip_init();
|
||||
#endif
|
||||
|
||||
/* route signals to GIC */
|
||||
iowrite32(0x0, pfc_inta_ctrl);
|
||||
|
||||
@ -576,11 +576,18 @@ void __init r8a7778_init_irq_extpin(int irlm)
|
||||
void __init r8a7778_init_irq_dt(void)
|
||||
{
|
||||
void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
|
||||
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
||||
void __iomem *gic_dist_base = ioremap_nocache(0xfe438000, 0x1000);
|
||||
void __iomem *gic_cpu_base = ioremap_nocache(0xfe430000, 0x1000);
|
||||
#endif
|
||||
|
||||
BUG_ON(!base);
|
||||
|
||||
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
#else
|
||||
irqchip_init();
|
||||
|
||||
#endif
|
||||
/* route all interrupts to ARM */
|
||||
__raw_writel(0x73ffffff, base + INT2NTSR0);
|
||||
__raw_writel(0xffffffff, base + INT2NTSR1);
|
||||
|
||||
@ -720,10 +720,17 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
|
||||
|
||||
void __init r8a7779_init_irq_dt(void)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
||||
void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
|
||||
void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
|
||||
#endif
|
||||
gic_arch_extn.irq_set_wake = r8a7779_set_wake;
|
||||
|
||||
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
#else
|
||||
irqchip_init();
|
||||
|
||||
#endif
|
||||
/* route all interrupts to ARM */
|
||||
__raw_writel(0xffffffff, INT2NTSR0);
|
||||
__raw_writel(0x3fffffff, INT2NTSR1);
|
||||
|
||||
@ -133,7 +133,9 @@ void __init rcar_gen2_timer_init(void)
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
rcar_gen2_clocks_init(mode);
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_SHMOBILE_MULTI
|
||||
clocksource_of_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
struct memory_reserve_config {
|
||||
|
||||
@ -595,6 +595,7 @@ static struct platform_device ipmmu_device = {
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin0_platform_data = {
|
||||
.irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
|
||||
.control_parent = true,
|
||||
};
|
||||
|
||||
static struct resource irqpin0_resources[] = {
|
||||
@ -656,6 +657,7 @@ static struct platform_device irqpin1_device = {
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin2_platform_data = {
|
||||
.irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
|
||||
.control_parent = true,
|
||||
};
|
||||
|
||||
static struct resource irqpin2_resources[] = {
|
||||
@ -686,6 +688,7 @@ static struct platform_device irqpin2_device = {
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin3_platform_data = {
|
||||
.irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
|
||||
.control_parent = true,
|
||||
};
|
||||
|
||||
static struct resource irqpin3_resources[] = {
|
||||
|
||||
@ -70,6 +70,18 @@ void __init shmobile_init_delay(void)
|
||||
if (!max_freq)
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
||||
/* Non-multiplatform r8a73a4 SoC cannot use arch timer due
|
||||
* to GIC being initialized from C and arch timer via DT */
|
||||
if (of_machine_is_compatible("renesas,r8a73a4"))
|
||||
has_arch_timer = false;
|
||||
|
||||
/* Non-multiplatform r8a7790 SoC cannot use arch timer due
|
||||
* to GIC being initialized from C and arch timer via DT */
|
||||
if (of_machine_is_compatible("renesas,r8a7790"))
|
||||
has_arch_timer = false;
|
||||
#endif
|
||||
|
||||
if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
|
||||
if (is_a7_a8_a9)
|
||||
shmobile_setup_delay_hz(max_freq, 1, 3);
|
||||
|
||||
@ -1940,18 +1940,8 @@ void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
|
||||
|
||||
/**
|
||||
* arm_iommu_attach_device
|
||||
* @dev: valid struct device pointer
|
||||
* @mapping: io address space mapping structure (returned from
|
||||
* arm_iommu_create_mapping)
|
||||
*
|
||||
* Attaches specified io address space mapping to the provided device,
|
||||
* More than one client might be attached to the same io address space
|
||||
* mapping.
|
||||
*/
|
||||
int arm_iommu_attach_device(struct device *dev,
|
||||
struct dma_iommu_mapping *mapping)
|
||||
static int __arm_iommu_attach_device(struct device *dev,
|
||||
struct dma_iommu_mapping *mapping)
|
||||
{
|
||||
int err;
|
||||
|
||||
@ -1965,15 +1955,35 @@ int arm_iommu_attach_device(struct device *dev,
|
||||
pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
|
||||
|
||||
/**
|
||||
* arm_iommu_detach_device
|
||||
* arm_iommu_attach_device
|
||||
* @dev: valid struct device pointer
|
||||
* @mapping: io address space mapping structure (returned from
|
||||
* arm_iommu_create_mapping)
|
||||
*
|
||||
* Detaches the provided device from a previously attached map.
|
||||
* Attaches specified io address space mapping to the provided device.
|
||||
* This replaces the dma operations (dma_map_ops pointer) with the
|
||||
* IOMMU aware version.
|
||||
*
|
||||
* More than one client might be attached to the same io address space
|
||||
* mapping.
|
||||
*/
|
||||
void arm_iommu_detach_device(struct device *dev)
|
||||
int arm_iommu_attach_device(struct device *dev,
|
||||
struct dma_iommu_mapping *mapping)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = __arm_iommu_attach_device(dev, mapping);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
set_dma_ops(dev, &iommu_ops);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
|
||||
|
||||
static void __arm_iommu_detach_device(struct device *dev)
|
||||
{
|
||||
struct dma_iommu_mapping *mapping;
|
||||
|
||||
@ -1989,6 +1999,19 @@ void arm_iommu_detach_device(struct device *dev)
|
||||
|
||||
pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
|
||||
}
|
||||
|
||||
/**
|
||||
* arm_iommu_detach_device
|
||||
* @dev: valid struct device pointer
|
||||
*
|
||||
* Detaches the provided device from a previously attached map.
|
||||
* This voids the dma operations (dma_map_ops pointer)
|
||||
*/
|
||||
void arm_iommu_detach_device(struct device *dev)
|
||||
{
|
||||
__arm_iommu_detach_device(dev);
|
||||
set_dma_ops(dev, NULL);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
|
||||
|
||||
static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
|
||||
@ -2011,7 +2034,7 @@ static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
|
||||
return false;
|
||||
}
|
||||
|
||||
if (arm_iommu_attach_device(dev, mapping)) {
|
||||
if (__arm_iommu_attach_device(dev, mapping)) {
|
||||
pr_warn("Failed to attached device %s to IOMMU_mapping\n",
|
||||
dev_name(dev));
|
||||
arm_iommu_release_mapping(mapping);
|
||||
@ -2025,7 +2048,7 @@ static void arm_teardown_iommu_dma_ops(struct device *dev)
|
||||
{
|
||||
struct dma_iommu_mapping *mapping = dev->archdata.mapping;
|
||||
|
||||
arm_iommu_detach_device(dev);
|
||||
__arm_iommu_detach_device(dev);
|
||||
arm_iommu_release_mapping(mapping);
|
||||
}
|
||||
|
||||
|
||||
@ -85,6 +85,7 @@ vdso_install:
|
||||
# We use MRPROPER_FILES and CLEAN_FILES now
|
||||
archclean:
|
||||
$(Q)$(MAKE) $(clean)=$(boot)
|
||||
$(Q)$(MAKE) $(clean)=$(boot)/dts
|
||||
|
||||
define archhelp
|
||||
echo '* Image.gz - Compressed kernel image (arch/$(ARCH)/boot/Image.gz)'
|
||||
|
||||
@ -3,6 +3,4 @@ dts-dirs += apm
|
||||
dts-dirs += arm
|
||||
dts-dirs += cavium
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &soc_uart0;
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
psci {
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user