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drm/amdgpu: Enable uvd and vce gpu re-init for SRIOV gpu reset
Add uvd and vce re-init after gpu reset. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1948,7 +1948,8 @@ static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
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AMD_IP_BLOCK_TYPE_DCE,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_IP_BLOCK_TYPE_SDMA,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_IP_BLOCK_TYPE_VCE
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};
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for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
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@ -894,9 +894,8 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
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table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
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header->uvd_table_size = table_size;
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return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
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}
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return -EINVAL; /* already initializaed ? */
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return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
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}
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/**
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@ -300,11 +300,9 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
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memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
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table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
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header->vce_table_size = table_size;
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return vce_v4_0_mmsch_start(adev, &adev->virt.mm_table);
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}
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return -EINVAL; /* already initializaed ? */
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return vce_v4_0_mmsch_start(adev, &adev->virt.mm_table);
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}
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/**
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