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net/mlx5e: Fix HW TS with CQE compression according to profile
When the driver's profile doesn't support a dedicated PTP-RQ, the PTP
accuracy of HW TS is affected by the CQE compression. In this case,
turn off CQE compression. Otherwise, the driver crashes:
BUG: kernel NULL pointer dereference, address:0000000000000018
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RIP: 0010:mlx5e_ptp_rx_set_fs+0x25/0x1a0 [mlx5_core]
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Call Trace:
mlx5e_ptp_activate_channel+0xb2/0xf0 [mlx5_core]
mlx5e_activate_priv_channels+0x3b9/0x8c0 [mlx5_core]
? __mutex_unlock_slowpath+0x45/0x2a0
? mlx5e_refresh_tirs+0x151/0x1e0 [mlx5_core]
mlx5e_switch_priv_channels+0x1cd/0x2d0 [mlx5_core]
? mlx5e_xdp_allowed+0x150/0x150 [mlx5_core]
mlx5e_safe_switch_params+0x118/0x3c0 [mlx5_core]
? __mutex_lock+0x6e/0x8e0
? mlx5e_hwstamp_set+0xa9/0x300 [mlx5_core]
mlx5e_hwstamp_set+0x194/0x300 [mlx5_core]
? dev_ioctl+0x9b/0x3d0
mlx5i_ioctl+0x37/0x60 [mlx5_core]
mlx5i_pkey_ioctl+0x12/0x20 [mlx5_core]
dev_ioctl+0xa9/0x3d0
sock_ioctl+0x268/0x420
__x64_sys_ioctl+0x3d8/0x790
? lockdep_hardirqs_on_prepare+0xe4/0x190
do_syscall_64+0x2d/0x40
entry_SYSCALL_64_after_hwframe+0x44/0xae
Fixes: 960fbfe222
("net/mlx5e: Allow coexistence of CQE compression and HW TS PTP")
Signed-off-by: Aya Levin <ayal@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
parent
2a2c84facd
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256f79d13c
@ -3984,11 +3984,45 @@ int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
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return mlx5e_ptp_rx_manage_fs(priv, set);
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}
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int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
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static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
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{
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bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
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int err;
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if (!rx_filter)
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/* Reset CQE compression to Admin default */
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return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);
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if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
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return 0;
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/* Disable CQE compression */
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netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
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err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
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if (err)
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netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
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return err;
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}
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static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
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{
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struct mlx5e_params new_params;
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if (ptp_rx == priv->channels.params.ptp_rx)
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return 0;
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new_params = priv->channels.params;
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new_params.ptp_rx = ptp_rx;
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return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
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&new_params.ptp_rx, true);
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}
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int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
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{
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struct hwtstamp_config config;
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bool rx_cqe_compress_def;
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bool ptp_rx;
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int err;
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if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
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@ -4008,13 +4042,12 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
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}
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mutex_lock(&priv->state_lock);
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new_params = priv->channels.params;
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rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
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/* RX HW timestamp */
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switch (config.rx_filter) {
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case HWTSTAMP_FILTER_NONE:
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new_params.ptp_rx = false;
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ptp_rx = false;
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break;
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case HWTSTAMP_FILTER_ALL:
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case HWTSTAMP_FILTER_SOME:
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@ -4031,24 +4064,25 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
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case HWTSTAMP_FILTER_PTP_V2_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
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case HWTSTAMP_FILTER_NTP_ALL:
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new_params.ptp_rx = rx_cqe_compress_def;
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config.rx_filter = HWTSTAMP_FILTER_ALL;
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/* ptp_rx is set if both HW TS is set and CQE
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* compression is set
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*/
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ptp_rx = rx_cqe_compress_def;
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break;
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default:
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mutex_unlock(&priv->state_lock);
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return -ERANGE;
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err = -ERANGE;
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goto err_unlock;
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}
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if (new_params.ptp_rx == priv->channels.params.ptp_rx)
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goto out;
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if (!priv->profile->rx_ptp_support)
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err = mlx5e_hwstamp_config_no_ptp_rx(priv,
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config.rx_filter != HWTSTAMP_FILTER_NONE);
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else
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err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
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if (err)
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goto err_unlock;
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err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
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&new_params.ptp_rx, true);
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if (err) {
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mutex_unlock(&priv->state_lock);
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return err;
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}
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out:
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memcpy(&priv->tstamp, &config, sizeof(config));
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mutex_unlock(&priv->state_lock);
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@ -4057,6 +4091,9 @@ out:
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return copy_to_user(ifr->ifr_data, &config,
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sizeof(config)) ? -EFAULT : 0;
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err_unlock:
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mutex_unlock(&priv->state_lock);
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return err;
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}
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int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
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