mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-16 09:34:22 +08:00
Merge tag 'qcom-arm64-for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/soc
Pull "Qualcomm ARM64 Updates for v4.15" from Andy Gross: * Add PCIE support to relevant MSM8996 based boards * Add RPM clock controller node on MSM8996 * Add dload address on MSM8916 and MSM8996 * Add MBHC button support on APQ8016 SBC * Add RTMFS specific compatible for rmtfs memory node * Fixups for MSM8916 GPIO line names and MDP address length * tag 'qcom-arm64-for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: msm8916: Mark rmtfs node as qcom, rmtfs-mem compatible arm64: dts: msm8996: Add the rpm clock controller node arm64: dts: qcom: sbc: Name GPIO lines arm64: dts: qcom: msm8916: Shrink mdp address length for msm8916 arm64: dts: apq8016-sbc: add mbhc buttons support arm64: dts: qcom: Specify dload address for msm8916 and msm8996 arm64: dts: apq8096-db820c: never disable regulator on LS expansion arm64: dts: apq8096-db820c: Enable on board 3 pcie root complex arm64: dts: qcom: msm8996: add support to pcie
This commit is contained in:
Arnd Bergmann
commit
2507514680
@ -19,6 +19,30 @@
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/sound/apq8016-lpass.h>
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/*
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* GPIO name legend: proper name = the GPIO line is used as GPIO
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* NC = not connected (pin out but not routed from the chip to
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* anything the board)
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* "[PER]" = pin is muxed for [peripheral] (not GPIO)
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* LSEC = Low Speed External Connector
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* HSEC = High Speed External Connector
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*
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* Line names are taken from the schematic "DragonBoard410c"
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* dated monday, august 31, 2015. Page 5 in particular.
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*
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* For the lines routed to the external connectors the
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* lines are named after the 96Boards CE Specification 1.0,
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* Appendix "Expansion Connector Signal Description".
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*
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* When the 96Board naming of a line and the schematic name of
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* the same line are in conflict, the 96Board specification
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* takes precedence, which means that the external UART on the
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* LSEC is named UART0 while the schematic and SoC names this
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* UART3. This is only for the informational lines i.e. "[FOO]",
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* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
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* ones actually used for GPIO.
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*/
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/ {
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aliases {
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serial0 = &blsp1_uart2;
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@ -47,6 +71,132 @@
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};
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soc {
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pinctrl@1000000 {
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gpio-line-names =
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"[UART0_TX]", /* GPIO_0, LSEC pin 5 */
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"[UART0_RX]", /* GPIO_1, LSEC pin 7 */
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"[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */
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"[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */
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"[UART1_TX]", /* GPIO_4, LSEC pin 11 */
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"[UART1_RX]", /* GPIO_5, LSEC pin 13 */
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"[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */
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"[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */
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"[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */
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"[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */
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"[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */
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"[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */
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"GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */
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"GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */
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"[I2C3_SDA]", /* HSEC pin 38 */
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"[I2C3_SCL]", /* HSEC pin 36 */
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"[SPI0_MOSI]", /* LSEC pin 14 */
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"[SPI0_MISO]", /* LSEC pin 10 */
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"[SPI0_CS_N]", /* LSEC pin 12 */
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"[SPI0_CLK]", /* LSEC pin 8 */
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"HDMI_HPD_N", /* GPIO 20 */
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"USR_LED_1_CTRL",
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"[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */
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"[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */
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"GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */
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"GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */
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"[CSI0_MCLK]", /* HSEC pin 15 */
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"[CSI1_MCLK]", /* HSEC pin 17 */
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"GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */
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"[I2C2_SDA]", /* HSEC pin 34 */
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"[I2C2_SCL]", /* HSEC pin 32 */
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"DSI2HDMI_INT_N",
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"DSI_SW_SEL_APQ",
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"GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */
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"GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */
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"GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */
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"GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */
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"FORCED_USB_BOOT",
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"SD_CARD_DET_N",
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"[WCSS_BT_SSBI]",
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"[WCSS_WLAN_DATA_2]", /* GPIO 40 */
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"[WCSS_WLAN_DATA_1]",
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"[WCSS_WLAN_DATA_0]",
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"[WCSS_WLAN_SET]",
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"[WCSS_WLAN_CLK]",
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"[WCSS_FM_SSBI]",
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"[WCSS_FM_SDI]",
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"[WCSS_BT_DAT_CTL]",
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"[WCSS_BT_DAT_STB]",
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"NC",
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"NC", /* GPIO 50 */
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC", /* GPIO 60 */
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"NC",
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"NC",
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"[CDC_PDM0_CLK]",
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"[CDC_PDM0_SYNC]",
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"[CDC_PDM0_TX0]",
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"[CDC_PDM0_RX0]",
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"[CDC_PDM0_RX1]",
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"[CDC_PDM0_RX2]",
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"GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */
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"NC", /* GPIO 70 */
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"NC",
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"NC",
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"NC",
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"NC", /* GPIO 74 */
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"BOOT_CONFIG_0", /* GPIO 80 */
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"BOOT_CONFIG_1",
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"BOOT_CONFIG_2",
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"BOOT_CONFIG_3",
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"NC",
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"NC",
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"BOOT_CONFIG_5",
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"NC",
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"NC",
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"NC",
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"NC", /* GPIO 90 */
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC", /* GPIO 100 */
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"NC",
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"NC",
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"NC",
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"SSBI_GPS",
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"NC",
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"NC",
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"KEY_VOLP_N",
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"NC",
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"NC",
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"[LS_EXP_MI2S_WS]", /* GPIO 110 */
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"NC",
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"NC",
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"[LS_EXP_MI2S_SCK]",
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"[LS_EXP_MI2S_DATA0]",
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"GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */
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"NC",
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"[DSI2HDMI_MI2S_WS]",
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"[DSI2HDMI_MI2S_SCK]",
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"[DSI2HDMI_MI2S_DATA0]",
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"USR_LED_2_CTRL", /* GPIO 120 */
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"SB_HS_ID";
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};
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dma@7884000 {
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status = "okay";
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};
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@ -329,6 +479,25 @@
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};
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};
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spmi@200f000 {
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pm8916@0 {
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gpios@c000 {
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gpio-line-names =
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"USR_LED_3_CTRL",
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"USR_LED_4_CTRL",
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"USB_HUB_RESET_N_PM",
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"USB_SW_SEL_PM";
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};
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mpps@a000 {
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gpio-line-names =
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"VDD_PX_BIAS",
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"WLAN_LED_CTRL",
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"BT_LED_CTRL",
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"GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */
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};
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};
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};
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wcnss@a21b000 {
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status = "okay";
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};
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@ -379,6 +548,8 @@
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status = "okay";
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clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
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clock-names = "mclk";
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qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
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qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
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};
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&smd_rpm_regulators {
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@ -138,6 +138,22 @@
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pinctrl-names = "default";
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pinctrl-0 = <&usb2_vbus_det_gpio>;
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};
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agnoc@0 {
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qcom,pcie@00600000 {
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perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
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};
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qcom,pcie@00608000 {
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status = "okay";
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perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
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};
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qcom,pcie@00610000 {
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status = "okay";
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perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
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};
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};
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};
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@ -173,9 +189,15 @@
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regulator-min-microvolt = <1300000>;
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regulator-max-microvolt = <1300000>;
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};
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/**
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* 1.8v required on LS expansion
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* for mezzanine boards
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*/
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s4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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s5 {
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regulator-min-microvolt = <2150000>;
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@ -69,8 +69,11 @@
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};
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rmtfs@86700000 {
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compatible = "qcom,rmtfs-mem";
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reg = <0x0 0x86700000 0x0 0xe0000>;
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no-map;
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qcom,client-id = <1>;
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};
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rfsa@867e00000 {
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@ -257,6 +260,8 @@
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clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
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clock-names = "core", "bus", "iface";
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#reset-cells = <1>;
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qcom,dload-mode = <&tcsr 0x6100>;
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};
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};
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@ -814,7 +819,7 @@
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mdp: mdp@1a01000 {
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compatible = "qcom,mdp5";
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reg = <0x1a01000 0x90000>;
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reg = <0x1a01000 0x89000>;
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reg-names = "mdp_phys";
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interrupt-parent = <&mdss>;
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@ -300,4 +300,199 @@
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drive-strength = <2>; /* 2 MA */
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};
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};
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pcie0_clkreq_default: pcie0_clkreq_default {
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mux {
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pins = "gpio36";
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function = "pci_e0";
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};
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config {
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pins = "gpio36";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie0_perst_default: pcie0_perst_default {
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mux {
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pins = "gpio35";
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function = "gpio";
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};
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config {
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pins = "gpio35";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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pcie0_wake_default: pcie0_wake_default {
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mux {
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pins = "gpio37";
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function = "gpio";
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};
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config {
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pins = "gpio37";
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drive-strength = <2>;
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bias-pull-up;
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};
|
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};
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pcie0_clkreq_sleep: pcie0_clkreq_sleep {
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mux {
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pins = "gpio36";
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function = "gpio";
|
||||
};
|
||||
|
||||
config {
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||||
pins = "gpio36";
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drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_wake_sleep: pcie0_wake_sleep {
|
||||
mux {
|
||||
pins = "gpio37";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio37";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_clkreq_default: pcie1_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio131";
|
||||
function = "pci_e1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio131";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_perst_default: pcie1_perst_default {
|
||||
mux {
|
||||
pins = "gpio130";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio130";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_wake_default: pcie1_wake_default {
|
||||
mux {
|
||||
pins = "gpio132";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio132";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_clkreq_sleep: pcie1_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio131";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio131";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_wake_sleep: pcie1_wake_sleep {
|
||||
mux {
|
||||
pins = "gpio132";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio132";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_clkreq_default: pcie2_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio115";
|
||||
function = "pci_e2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio115";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_perst_default: pcie2_perst_default {
|
||||
mux {
|
||||
pins = "gpio114";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio114";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_wake_default: pcie2_wake_default {
|
||||
mux {
|
||||
pins = "gpio116";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio116";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_clkreq_sleep: pcie2_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio115";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio115";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_wake_sleep: pcie2_wake_sleep {
|
||||
mux {
|
||||
pins = "gpio116";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio116";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
|
||||
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. MSM8996";
|
||||
@ -261,6 +262,8 @@
|
||||
firmware {
|
||||
scm {
|
||||
compatible = "qcom,scm-msm8996";
|
||||
|
||||
qcom,dload-mode = <&tcsr 0x13000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -289,6 +292,11 @@
|
||||
compatible = "qcom,rpm-msm8996";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
rpmcc: qcom,rpmcc {
|
||||
compatible = "qcom,rpmcc-msm8996";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pm8994-regulators {
|
||||
compatible = "qcom,rpm-pm8994-regulators";
|
||||
|
||||
@ -358,6 +366,11 @@
|
||||
reg = <0x740000 0x20000>;
|
||||
};
|
||||
|
||||
tcsr: syscon@7a0000 {
|
||||
compatible = "qcom,tcsr-msm8996", "syscon";
|
||||
reg = <0x7a0000 0x18000>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@9bc0000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
@ -819,6 +832,172 @@
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
};
|
||||
};
|
||||
|
||||
agnoc@0 {
|
||||
power-domains = <&gcc AGGRE0_NOC_GDSC>;
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pcie0: qcom,pcie@00600000 {
|
||||
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
||||
status = "disabled";
|
||||
power-domains = <&gcc PCIE0_GDSC>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
|
||||
reg = <0x00600000 0x2000>,
|
||||
<0x0c000000 0xf1d>,
|
||||
<0x0c000f20 0xa8>,
|
||||
<0x0c100000 0x100000>;
|
||||
reg-names = "parf", "dbi", "elbi","config";
|
||||
|
||||
phys = <&pciephy_0>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
|
||||
|
||||
interrupts = <GIC_SPI 405 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
|
||||
pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
|
||||
|
||||
|
||||
vdda-supply = <&pm8994_l28>;
|
||||
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
|
||||
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave";
|
||||
|
||||
};
|
||||
|
||||
pcie1: qcom,pcie@00608000 {
|
||||
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
||||
power-domains = <&gcc PCIE1_GDSC>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
reg = <0x00608000 0x2000>,
|
||||
<0x0d000000 0xf1d>,
|
||||
<0x0d000f20 0xa8>,
|
||||
<0x0d100000 0x100000>;
|
||||
|
||||
reg-names = "parf", "dbi", "elbi","config";
|
||||
|
||||
phys = <&pciephy_1>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
|
||||
|
||||
interrupts = <GIC_SPI 413 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
|
||||
pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
|
||||
|
||||
|
||||
vdda-supply = <&pm8994_l28>;
|
||||
linux,pci-domain = <1>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_1_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
|
||||
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave";
|
||||
};
|
||||
|
||||
pcie2: qcom,pcie@00610000 {
|
||||
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
||||
power-domains = <&gcc PCIE2_GDSC>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
status = "disabled";
|
||||
reg = <0x00610000 0x2000>,
|
||||
<0x0e000000 0xf1d>,
|
||||
<0x0e000f20 0xa8>,
|
||||
<0x0e100000 0x100000>;
|
||||
|
||||
reg-names = "parf", "dbi", "elbi","config";
|
||||
|
||||
phys = <&pciephy_2>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
|
||||
|
||||
device_type = "pci";
|
||||
|
||||
interrupts = <GIC_SPI 421 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
|
||||
pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
|
||||
|
||||
vdda-supply = <&pm8994_l28>;
|
||||
|
||||
linux,pci-domain = <2>;
|
||||
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_2_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
|
||||
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
adsp-pil {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user