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powerpc/cell: Remove the Cell QPACE code
All users of QPACE have upgraded to QPACE2 so remove the Cell QPACE code. Signed-off-by: Rashmica Gupta <rashmicy@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Rashmica Gupta
Michael Ellerman
parent
b4af279a7c
commit
24ad1648ed
@ -14,7 +14,6 @@ Required properties:
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tegra132, or tegra210.
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- "nxp,lpc3220-uart"
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- "ralink,rt2880-uart"
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- "ibm,qpace-nwp-serial"
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- "altr,16550-FIFO32"
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- "altr,16550-FIFO64"
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- "altr,16550-FIFO128"
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@ -113,7 +113,6 @@ src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
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src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
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src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
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src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
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src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S
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src-wlib := $(sort $(src-wlib-y))
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src-plat := $(sort $(src-plat-y))
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@ -217,7 +216,6 @@ image-$(CONFIG_PPC_POWERNV) += zImage.pseries
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image-$(CONFIG_PPC_MAPLE) += zImage.maple
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image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries
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image-$(CONFIG_PPC_PS3) += dtbImage.ps3
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image-$(CONFIG_PPC_CELL_QPACE) += zImage.pseries
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image-$(CONFIG_PPC_CHRP) += zImage.chrp
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image-$(CONFIG_PPC_EFIKA) += zImage.chrp
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image-$(CONFIG_PPC_PMAC) += zImage.pmac
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@ -36,7 +36,6 @@ CONFIG_PS3_ROM=m
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CONFIG_PS3_FLASH=m
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CONFIG_PS3_LPM=m
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CONFIG_PPC_IBM_CELL_BLADE=y
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CONFIG_PPC_CELL_QPACE=y
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CONFIG_RTAS_FLASH=m
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CONFIG_IBMEBUS=y
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CONFIG_CPU_FREQ_PMAC64=y
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@ -33,11 +33,6 @@ config PPC_IBM_CELL_BLADE
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select PPC_UDBG_16550
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select UDBG_RTAS_CONSOLE
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config PPC_CELL_QPACE
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bool "IBM Cell - QPACE"
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depends on PPC64 && PPC_BOOK3S && CPU_BIG_ENDIAN
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select PPC_CELL_COMMON
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config AXON_MSI
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bool
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depends on PPC_IBM_CELL_BLADE && PCI_MSI
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@ -11,7 +11,6 @@ obj-$(CONFIG_PPC_IBM_CELL_POWERBUTTON) += cbe_powerbutton.o
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ifeq ($(CONFIG_SMP),y)
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obj-$(CONFIG_PPC_CELL_NATIVE) += smp.o
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obj-$(CONFIG_PPC_CELL_QPACE) += smp.o
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endif
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# needed only when building loadable spufs.ko
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@ -26,6 +25,3 @@ obj-$(CONFIG_SPU_BASE) += spu_callbacks.o spu_base.o \
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spufs/
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obj-$(CONFIG_AXON_MSI) += axon_msi.o
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# qpace setup
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obj-$(CONFIG_PPC_CELL_QPACE) += qpace_setup.o
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@ -1,148 +0,0 @@
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/*
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* linux/arch/powerpc/platforms/cell/qpace_setup.c
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*
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* Copyright (C) 1995 Linus Torvalds
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* Adapted from 'alpha' version by Gary Thomas
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* Modified by PPC64 Team, IBM Corp
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* Modified by Cell Team, IBM Deutschland Entwicklung GmbH
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* Modified by Benjamin Krill <ben@codiert.org>, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/console.h>
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#include <linux/of_platform.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/kexec.h>
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#include <asm/pgtable.h>
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#include <asm/prom.h>
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#include <asm/rtas.h>
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#include <asm/dma.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <asm/cputable.h>
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#include <asm/irq.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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#include <asm/udbg.h>
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#include <asm/cell-regs.h>
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#include "interrupt.h"
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#include "pervasive.h"
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#include "ras.h"
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static void qpace_show_cpuinfo(struct seq_file *m)
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{
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struct device_node *root;
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const char *model = "";
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root = of_find_node_by_path("/");
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if (root)
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model = of_get_property(root, "model", NULL);
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seq_printf(m, "machine\t\t: CHRP %s\n", model);
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of_node_put(root);
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}
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static void qpace_progress(char *s, unsigned short hex)
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{
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printk("*** %04x : %s\n", hex, s ? s : "");
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}
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static const struct of_device_id qpace_bus_ids[] __initconst = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .type = "spider", },
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{ .type = "axon", },
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{ .type = "plb5", },
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{ .type = "plb4", },
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{ .type = "opb", },
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{ .type = "ebc", },
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{},
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};
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static int __init qpace_publish_devices(void)
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{
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int node;
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/* Publish OF platform devices for southbridge IOs */
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of_platform_bus_probe(NULL, qpace_bus_ids, NULL);
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/* There is no device for the MIC memory controller, thus we create
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* a platform device for it to attach the EDAC driver to.
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*/
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for_each_online_node(node) {
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if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
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continue;
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platform_device_register_simple("cbe-mic", node, NULL, 0);
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}
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return 0;
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}
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machine_subsys_initcall(qpace, qpace_publish_devices);
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static void __init qpace_setup_arch(void)
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{
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#ifdef CONFIG_SPU_BASE
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spu_priv1_ops = &spu_priv1_mmio_ops;
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spu_management_ops = &spu_management_of_ops;
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#endif
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cbe_regs_init();
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#ifdef CONFIG_CBE_RAS
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cbe_ras_init();
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#endif
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#ifdef CONFIG_SMP
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smp_init_cell();
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#endif
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000;
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cbe_pervasive_init();
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#ifdef CONFIG_DUMMY_CONSOLE
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conswitchp = &dummy_con;
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#endif
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}
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static int __init qpace_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (!of_flat_dt_is_compatible(root, "IBM,QPACE"))
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return 0;
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hpte_init_native();
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pm_power_off = rtas_power_off;
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return 1;
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}
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define_machine(qpace) {
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.name = "QPACE",
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.probe = qpace_probe,
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.setup_arch = qpace_setup_arch,
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.show_cpuinfo = qpace_show_cpuinfo,
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.restart = rtas_restart,
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.halt = rtas_halt,
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.get_boot_time = rtas_get_boot_time,
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.get_rtc_time = rtas_get_rtc_time,
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.set_rtc_time = rtas_set_rtc_time,
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.calibrate_decr = generic_calibrate_decr,
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.progress = qpace_progress,
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.init_IRQ = iic_init_IRQ,
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};
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