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ahci: imx: add namespace for register enums
Update register enums a little bit to add proper namespace prefix, and have the names match i.MX reference manual. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
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@ -29,9 +29,11 @@
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#include "ahci.h"
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enum {
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PORT_PHY_CTL = 0x178, /* Port0 PHY Control */
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PORT_PHY_CTL_PDDQ_LOC = 0x100000, /* PORT_PHY_CTL bits */
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HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
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/* Timer 1-ms Register */
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IMX_TIMER1MS = 0x00e0,
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/* Port0 PHY Control Register */
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IMX_P0PHYCR = 0x0178,
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IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
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};
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enum ahci_imx_type {
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@ -156,8 +158,8 @@ static void ahci_imx_error_handler(struct ata_port *ap)
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* without full reset once the pddq mode is enabled making it
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* impossible to use as part of libata LPM.
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*/
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reg_val = readl(mmio + PORT_PHY_CTL);
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writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
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reg_val = readl(mmio + IMX_P0PHYCR);
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writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
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imx_sata_disable(hpriv);
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imxpriv->no_device = true;
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}
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@ -248,7 +250,7 @@ static int imx_ahci_probe(struct platform_device *pdev)
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/*
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* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
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* and IP vendor specific register HOST_TIMER1MS.
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* and IP vendor specific register IMX_TIMER1MS.
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* Configure CAP_SSS (support stagered spin up).
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* Implement the port0.
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* Get the ahb clock rate, and configure the TIMER1MS register.
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@ -265,7 +267,7 @@ static int imx_ahci_probe(struct platform_device *pdev)
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}
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reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
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writel(reg_val, hpriv->mmio + HOST_TIMER1MS);
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writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
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ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0);
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if (ret)
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