renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-17 09:43:59 +08:00
Code

Merge tag 'drm-intel-fixes-2015-07-31' of git://anongit.freedesktop.org/drm-intel

Browse Source 
Pull drm intel fixes from Daniel Vetter:
 "I delayed my -fixes pull a bit hoping that I could include a fix for
  the dp mst stuff but looks a bit more nasty than that.  So just 3
  other regression fixes, one 4.2 other two cc: stable"

* tag 'drm-intel-fixes-2015-07-31' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Declare the swizzling unknown for L-shaped configurations
  drm/i915: Mark PIN_USER binding as GLOBAL_BIND without the aliasing ppgtt
  drm/i915: Replace WARN inside I915_READ64_2x32 with retry loop
This commit is contained in:
Linus Torvalds 2015-07-31 12:11:01 -07:00
commit 23ff9e19fe
3 changed files with 23 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/gpu/drm/i915/i915_drv.h
View File

@ -3303,15 +3303,14 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
#define I915_READ64_2x32(lower_reg, upper_reg) ({ \ #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
u32 upper = I915_READ(upper_reg); \ u32 upper, lower, tmp; \
u32 lower = I915_READ(lower_reg); \ tmp = I915_READ(upper_reg); \
u32 tmp = I915_READ(upper_reg); \ do { \
if (upper != tmp) { \ upper = tmp; \
upper = tmp; \ lower = I915_READ(lower_reg); \
lower = I915_READ(lower_reg); \ tmp = I915_READ(upper_reg); \
WARN_ON(I915_READ(upper_reg) != upper); \ } while (upper != tmp); \
} \ (u64)upper << 32 | lower; })
(u64)upper << 32 | lower; })
#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)

11
drivers/gpu/drm/i915/i915_gem_gtt.c
View File

@ -1923,6 +1923,17 @@ static int ggtt_bind_vma(struct i915_vma *vma,
vma->vm->insert_entries(vma->vm, pages, vma->vm->insert_entries(vma->vm, pages,
vma->node.start, vma->node.start,
cache_level, pte_flags); cache_level, pte_flags);
/* Note the inconsistency here is due to absence of the
* aliasing ppgtt on gen4 and earlier. Though we always
* request PIN_USER for execbuffer (translated to LOCAL_BIND),
* without the appgtt, we cannot honour that request and so
* must substitute it with a global binding. Since we do this
* behind the upper layers back, we need to explicitly set
* the bound flag ourselves.
*/
vma->bound |= GLOBAL_BIND;
} }
if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) { if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {

5
drivers/gpu/drm/i915/i915_gem_tiling.c
View File

@ -464,7 +464,10 @@ i915_gem_get_tiling(struct drm_device *dev, void *data,
} }
/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
args->phys_swizzle_mode = args->swizzle_mode; if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
else
args->phys_swizzle_mode = args->swizzle_mode;
if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
args->swizzle_mode = I915_BIT_6_SWIZZLE_9; args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)