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ASoC: Don't use write sequencer to power up WM8903

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The write sequencer sequencer sequence takes longer than is desirable
as it brings up a full playback path which is not required at this
point. Open coding the sequence cuts the startup time by two thirds.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
This commit is contained in:
Mark Brown 2011-02-10 14:01:38 +00:00
parent 66daaa59d5
commit 22f226dd14
1 changed files with 52 additions and 17 deletions
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69
sound/soc/codecs/wm8903.c
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@ -297,15 +297,6 @@ static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
return 0; return 0;
} }
static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
{
int i;
/* There really ought to be something better we can do here :/ */
for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
cache[i] = codec->hw_read(codec, i);
}
static void wm8903_reset(struct snd_soc_codec *codec) static void wm8903_reset(struct snd_soc_codec *codec)
{ {
snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0); snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
@ -1142,6 +1133,7 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec,
switch (level) { switch (level) {
case SND_SOC_BIAS_ON: case SND_SOC_BIAS_ON:
break; break;
case SND_SOC_BIAS_PREPARE: case SND_SOC_BIAS_PREPARE:
snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
WM8903_VMID_RES_MASK, WM8903_VMID_RES_MASK,
@ -1150,16 +1142,59 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec,
case SND_SOC_BIAS_STANDBY: case SND_SOC_BIAS_STANDBY:
if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
snd_soc_write(codec, WM8903_CLOCK_RATES_2, snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
WM8903_CLK_SYS_ENA); WM8903_POBCTRL | WM8903_ISEL_MASK |
WM8903_STARTUP_BIAS_ENA |
WM8903_BIAS_ENA,
WM8903_POBCTRL |
(2 << WM8903_ISEL_SHIFT) |
WM8903_STARTUP_BIAS_ENA);
/* Change DC servo dither level in startup sequence */ snd_soc_update_bits(codec,
snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11); WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257); WM8903_SPK_DISCHARGE,
snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2); WM8903_SPK_DISCHARGE);
wm8903_run_sequence(codec, 0); msleep(33);
wm8903_sync_reg_cache(codec, codec->reg_cache);
snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
WM8903_SPKL_ENA | WM8903_SPKR_ENA,
WM8903_SPKL_ENA | WM8903_SPKR_ENA);
snd_soc_update_bits(codec,
WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
WM8903_SPK_DISCHARGE, 0);
snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
WM8903_VMID_TIE_ENA |
WM8903_BUFIO_ENA |
WM8903_VMID_IO_ENA |
WM8903_VMID_SOFT_MASK |
WM8903_VMID_RES_MASK |
WM8903_VMID_BUF_ENA,
WM8903_VMID_TIE_ENA |
WM8903_BUFIO_ENA |
WM8903_VMID_IO_ENA |
(2 << WM8903_VMID_SOFT_SHIFT) |
WM8903_VMID_RES_250K |
WM8903_VMID_BUF_ENA);
msleep(129);
snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
WM8903_SPKL_ENA | WM8903_SPKR_ENA,
0);
snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
WM8903_VMID_SOFT_MASK, 0);
snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
WM8903_VMID_RES_MASK,
WM8903_VMID_RES_50K);
snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
WM8903_BIAS_ENA | WM8903_POBCTRL,
WM8903_BIAS_ENA);
/* By default no bypass paths are enabled so /* By default no bypass paths are enabled so
* enable Class W support. * enable Class W support.