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https://github.com/edk2-porting/linux-next.git
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amd64_edac: Check ECC capabilities initially
Rework the code to check the hardware ECC capabilities at PCI probing time. We do all further initialization only if we actually can/have ECC enabled. While at it: 0. Fix function naming. 1. Simplify/clarify debug output. 2. Remove amd64_ prefix from the static functions 3. Reorganize code. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
parent
ae7bb7c679
commit
2299ef7114
@ -2188,18 +2188,19 @@ static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt)
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static int amd64_init_csrows(struct mem_ctl_info *mci)
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{
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struct csrow_info *csrow;
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struct amd64_pvt *pvt;
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struct amd64_pvt *pvt = mci->pvt_info;
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u64 input_addr_min, input_addr_max, sys_addr;
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u32 val;
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int i, empty = 1;
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pvt = mci->pvt_info;
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amd64_read_pci_cfg(pvt->F3, K8_NBCFG, &val);
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amd64_read_pci_cfg(pvt->F3, K8_NBCFG, &pvt->nbcfg);
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pvt->nbcfg = val;
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pvt->ctl_error_info.nbcfg = val;
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debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt->nbcfg,
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(pvt->nbcfg & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
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(pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"
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);
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debugf0("node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
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pvt->mc_node_id, val,
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!!(val & K8_NBCFG_CHIPKILL), !!(val & K8_NBCFG_ECC_ENABLE));
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for (i = 0; i < pvt->cs_count; i++) {
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csrow = &mci->csrows[i];
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@ -2294,7 +2295,7 @@ out:
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return ret;
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}
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static int amd64_toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on)
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static int toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on)
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{
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cpumask_var_t cmask;
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int cpu;
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@ -2332,30 +2333,31 @@ static int amd64_toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool o
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return 0;
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}
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static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
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static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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struct pci_dev *F3)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u8 nid = pvt->mc_node_id;
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struct ecc_settings *s = ecc_stngs[nid];
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bool ret = true;
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u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
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amd64_read_pci_cfg(pvt->F3, K8_NBCTL, &value);
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if (toggle_ecc_err_reporting(s, nid, ON)) {
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amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
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return false;
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}
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amd64_read_pci_cfg(F3, K8_NBCTL, &value);
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/* turn on UECCEn and CECCEn bits */
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s->old_nbctl = value & mask;
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s->nbctl_valid = true;
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value |= mask;
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pci_write_config_dword(pvt->F3, K8_NBCTL, value);
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pci_write_config_dword(F3, K8_NBCTL, value);
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if (amd64_toggle_ecc_err_reporting(s, nid, ON))
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amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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amd64_read_pci_cfg(pvt->F3, K8_NBCFG, &value);
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debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
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(value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
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(value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
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debugf0("1: node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
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nid, value,
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!!(value & K8_NBCFG_CHIPKILL), !!(value & K8_NBCFG_ECC_ENABLE));
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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amd64_warn("DRAM ECC disabled on this node, enabling...\n");
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@ -2364,13 +2366,14 @@ static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
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/* Attempt to turn on DRAM ECC Enable */
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value |= K8_NBCFG_ECC_ENABLE;
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pci_write_config_dword(pvt->F3, K8_NBCFG, value);
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pci_write_config_dword(F3, K8_NBCFG, value);
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amd64_read_pci_cfg(pvt->F3, K8_NBCFG, &value);
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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amd64_warn("Hardware rejected DRAM ECC enable,"
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"check memory DIMM configuration.\n");
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ret = false;
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} else {
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amd64_info("Hardware accepted DRAM ECC Enable\n");
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}
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@ -2378,11 +2381,11 @@ static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
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s->flags.nb_ecc_prev = 1;
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}
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debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
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(value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
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(value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
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debugf0("2: node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
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nid, value,
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!!(value & K8_NBCFG_CHIPKILL), !!(value & K8_NBCFG_ECC_ENABLE));
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pvt->ctl_error_info.nbcfg = value;
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return ret;
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}
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static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
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@ -2408,15 +2411,15 @@ static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
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}
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/* restore the NB Enable MCGCTL bit */
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if (amd64_toggle_ecc_err_reporting(s, nid, OFF))
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if (toggle_ecc_err_reporting(s, nid, OFF))
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amd64_warn("Error restoring NB MCGCTL settings!\n");
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}
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/*
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* EDAC requires that the BIOS have ECC enabled before taking over the
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* processing of ECC errors. This is because the BIOS can properly initialize
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* the memory system completely. A command line option allows to force-enable
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* hardware ECC later in amd64_enable_ecc_error_reporting().
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* EDAC requires that the BIOS have ECC enabled before
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* taking over the processing of ECC errors. A command line
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* option allows to force-enable hardware ECC later in
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* enable_ecc_error_reporting().
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*/
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static const char *ecc_msg =
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"ECC disabled in the BIOS or no ECC capability, module will not load.\n"
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@ -2424,33 +2427,28 @@ static const char *ecc_msg =
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"'ecc_enable_override'.\n"
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" (Note that use of the override may cause unknown side effects.)\n";
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static int amd64_check_ecc_enabled(struct amd64_pvt *pvt)
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static bool ecc_enabled(struct pci_dev *F3, u8 nid)
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{
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u32 value;
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u8 ecc_enabled = 0;
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u8 ecc_en = 0;
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bool nb_mce_en = false;
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amd64_read_pci_cfg(pvt->F3, K8_NBCFG, &value);
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE);
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amd64_info("DRAM ECC %s.\n", (ecc_enabled ? "enabled" : "disabled"));
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ecc_en = !!(value & K8_NBCFG_ECC_ENABLE);
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amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled"));
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nb_mce_en = amd64_nb_mce_bank_enabled_on_node(pvt->mc_node_id);
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nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid);
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if (!nb_mce_en)
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amd64_notice("NB MCE bank disabled, "
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"set MSR 0x%08x[4] on node %d to enable.\n",
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MSR_IA32_MCG_CTL, pvt->mc_node_id);
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amd64_notice("NB MCE bank disabled, set MSR "
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"0x%08x[4] on node %d to enable.\n",
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MSR_IA32_MCG_CTL, nid);
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if (!ecc_enabled || !nb_mce_en) {
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if (!ecc_enable_override) {
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amd64_notice("%s", ecc_msg);
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return -ENODEV;
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} else {
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amd64_warn("Forcing ECC on!\n");
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}
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if (!ecc_en || !nb_mce_en) {
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amd64_notice("%s", ecc_msg);
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return false;
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}
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return 0;
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return true;
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}
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struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) +
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@ -2536,7 +2534,7 @@ static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt)
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return fam_type;
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}
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static int amd64_probe_one_instance(struct pci_dev *F2)
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static int amd64_init_one_instance(struct pci_dev *F2)
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{
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struct amd64_pvt *pvt = NULL;
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struct amd64_family_type *fam_type = NULL;
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@ -2561,11 +2559,6 @@ static int amd64_probe_one_instance(struct pci_dev *F2)
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if (err)
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goto err_free;
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ret = -EINVAL;
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err = amd64_check_ecc_enabled(pvt);
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if (err)
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goto err_put;
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/*
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* Save the pointer to the private data for use in 2nd initialization
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* stage
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@ -2574,9 +2567,6 @@ static int amd64_probe_one_instance(struct pci_dev *F2)
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return 0;
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err_put:
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amd64_free_mc_sibling_devices(pvt);
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err_free:
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kfree(pvt);
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@ -2618,7 +2608,6 @@ static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
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if (amd64_init_csrows(mci))
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mci->edac_cap = EDAC_FLAG_NONE;
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amd64_enable_ecc_error_reporting(mci);
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amd64_set_mc_sysfs_attributes(mci);
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ret = -ENODEV;
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@ -2655,12 +2644,13 @@ err_exit:
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}
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static int __devinit amd64_init_one_instance(struct pci_dev *pdev,
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static int __devinit amd64_probe_one_instance(struct pci_dev *pdev,
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const struct pci_device_id *mc_type)
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{
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int ret = 0;
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u8 nid = get_node_id(pdev);
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struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
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struct ecc_settings *s;
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int ret = 0;
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ret = pci_enable_device(pdev);
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if (ret < 0) {
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@ -2671,15 +2661,34 @@ static int __devinit amd64_init_one_instance(struct pci_dev *pdev,
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ret = -ENOMEM;
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s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
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if (!s)
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return ret;
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goto err_out;
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ecc_stngs[nid] = s;
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ret = amd64_probe_one_instance(pdev);
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if (!ecc_enabled(F3, nid)) {
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ret = -ENODEV;
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if (!ecc_enable_override)
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goto err_enable;
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amd64_warn("Forcing ECC on!\n");
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if (!enable_ecc_error_reporting(s, nid, F3))
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goto err_enable;
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}
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ret = amd64_init_one_instance(pdev);
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if (ret < 0)
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amd64_err("Error probing instance: %d\n", nid);
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return ret;
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err_enable:
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kfree(s);
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ecc_stngs[nid] = NULL;
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err_out:
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return ret;
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}
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static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
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@ -2741,7 +2750,7 @@ MODULE_DEVICE_TABLE(pci, amd64_pci_table);
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static struct pci_driver amd64_pci_driver = {
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.name = EDAC_MOD_STR,
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.probe = amd64_init_one_instance,
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.probe = amd64_probe_one_instance,
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.remove = __devexit_p(amd64_remove_one_instance),
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.id_table = amd64_pci_table,
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};
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