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https://github.com/edk2-porting/linux-next.git
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gpio: mvebu: switch to regmap for register access
In order to be able to use this driver with the Armada 7K/8K SoCs, we need to use the regmap to access the registers. Indeed for these new SoCs, the gpio node will be part of a syscon. [gregory.clement@free-electrons.com: - fixed merge conflcit from 4.10 to 4.12-rc1 - added a commit log] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Thomas Petazzoni
Linus Walleij
parent
6ec015d613
commit
2233bf7a92
@ -47,6 +47,7 @@
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "gpiolib.h"
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@ -106,9 +107,8 @@ struct mvebu_pwm {
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struct mvebu_gpio_chip {
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struct gpio_chip chip;
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spinlock_t lock;
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void __iomem *membase;
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void __iomem *percpu_membase;
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struct regmap *regs;
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struct regmap *percpu_regs;
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int irqbase;
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struct irq_domain *domain;
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int soc_variant;
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@ -130,92 +130,149 @@ struct mvebu_gpio_chip {
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* Functions returning addresses of individual registers for a given
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* GPIO controller.
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*/
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static void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_OUT_OFF;
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}
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static void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_BLINK_EN_OFF;
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}
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static void __iomem *mvebu_gpioreg_blink_counter_select(struct mvebu_gpio_chip
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*mvchip)
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{
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return mvchip->membase + GPIO_BLINK_CNT_SELECT_OFF;
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}
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static void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_IO_CONF_OFF;
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}
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static void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_IN_POL_OFF;
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}
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static void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_DATA_IN_OFF;
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}
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static void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
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static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
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struct regmap **map, unsigned int *offset)
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{
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int cpu;
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switch (mvchip->soc_variant) {
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case MVEBU_GPIO_SOC_VARIANT_ORION:
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case MVEBU_GPIO_SOC_VARIANT_MV78200:
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return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
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*map = mvchip->regs;
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*offset = GPIO_EDGE_CAUSE_OFF;
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break;
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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return mvchip->percpu_membase +
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GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
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*map = mvchip->percpu_regs;
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*offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
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break;
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default:
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BUG();
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}
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}
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static void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
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static u32
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mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
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{
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struct regmap *map;
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unsigned int offset;
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u32 val;
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mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
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regmap_read(map, offset, &val);
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return val;
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}
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static void
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mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
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{
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struct regmap *map;
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unsigned int offset;
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mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
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regmap_write(map, offset, val);
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}
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static inline void
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mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
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struct regmap **map, unsigned int *offset)
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{
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int cpu;
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switch (mvchip->soc_variant) {
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case MVEBU_GPIO_SOC_VARIANT_ORION:
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return mvchip->membase + GPIO_EDGE_MASK_OFF;
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*map = mvchip->regs;
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*offset = GPIO_EDGE_MASK_OFF;
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break;
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case MVEBU_GPIO_SOC_VARIANT_MV78200:
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cpu = smp_processor_id();
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return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
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*map = mvchip->regs;
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*offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
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break;
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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return mvchip->percpu_membase +
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GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
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*map = mvchip->percpu_regs;
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*offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
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break;
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default:
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BUG();
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}
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}
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static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
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static u32
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mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
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{
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struct regmap *map;
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unsigned int offset;
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u32 val;
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mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
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regmap_read(map, offset, &val);
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return val;
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}
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static void
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mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
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{
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struct regmap *map;
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unsigned int offset;
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mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
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regmap_write(map, offset, val);
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}
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static void
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mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
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struct regmap **map, unsigned int *offset)
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{
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int cpu;
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switch (mvchip->soc_variant) {
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case MVEBU_GPIO_SOC_VARIANT_ORION:
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return mvchip->membase + GPIO_LEVEL_MASK_OFF;
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*map = mvchip->regs;
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*offset = GPIO_LEVEL_MASK_OFF;
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break;
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case MVEBU_GPIO_SOC_VARIANT_MV78200:
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cpu = smp_processor_id();
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return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
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*map = mvchip->regs;
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*offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
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break;
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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return mvchip->percpu_membase +
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GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
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*map = mvchip->percpu_regs;
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*offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
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break;
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default:
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BUG();
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}
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}
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static u32
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mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
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{
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struct regmap *map;
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unsigned int offset;
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u32 val;
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mvebu_gpioreg_level_mask(mvchip, &map, &offset);
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regmap_read(map, offset, &val);
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return val;
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}
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static void
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mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
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{
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struct regmap *map;
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unsigned int offset;
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mvebu_gpioreg_level_mask(mvchip, &map, &offset);
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regmap_write(map, offset, val);
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}
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/*
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* Functions returning addresses of individual registers for a given
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* PWM controller.
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@ -236,17 +293,9 @@ static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
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static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
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{
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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unsigned long flags;
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u32 u;
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_out(mvchip));
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if (value)
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u |= BIT(pin);
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else
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u &= ~BIT(pin);
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writel_relaxed(u, mvebu_gpioreg_out(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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regmap_update_bits(mvchip->regs, GPIO_OUT_OFF,
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BIT(pin), value ? BIT(pin) : 0);
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}
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static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
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@ -254,11 +303,16 @@ static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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u32 u;
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if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin)) {
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u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
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readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
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regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &u);
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if (u & BIT(pin)) {
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u32 data_in, in_pol;
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regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
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regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol);
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u = data_in ^ in_pol;
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} else {
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u = readl_relaxed(mvebu_gpioreg_out(mvchip));
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regmap_read(mvchip->regs, GPIO_OUT_OFF, &u);
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}
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return (u >> pin) & 1;
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@ -268,25 +322,15 @@ static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
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int value)
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{
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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unsigned long flags;
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u32 u;
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
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if (value)
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u |= BIT(pin);
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else
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u &= ~BIT(pin);
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writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF,
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BIT(pin), value ? BIT(pin) : 0);
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}
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static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
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{
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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unsigned long flags;
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int ret;
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u32 u;
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/*
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* Check with the pinctrl driver whether this pin is usable as
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@ -296,11 +340,8 @@ static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
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if (ret)
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return ret;
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
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u |= BIT(pin);
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writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
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BIT(pin), 1);
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return 0;
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}
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@ -309,9 +350,7 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
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int value)
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{
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struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
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unsigned long flags;
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int ret;
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u32 u;
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/*
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* Check with the pinctrl driver whether this pin is usable as
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@ -324,11 +363,8 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
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mvebu_gpio_blink(chip, pin, 0);
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mvebu_gpio_set(chip, pin, value);
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
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u &= ~BIT(pin);
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writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
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BIT(pin), 0);
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return 0;
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}
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@ -350,7 +386,7 @@ static void mvebu_gpio_irq_ack(struct irq_data *d)
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u32 mask = d->mask;
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irq_gc_lock(gc);
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writel_relaxed(~mask, mvebu_gpioreg_edge_cause(mvchip));
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mvebu_gpio_write_edge_cause(mvchip, ~mask);
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irq_gc_unlock(gc);
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}
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@ -363,8 +399,7 @@ static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
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irq_gc_lock(gc);
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ct->mask_cache_priv &= ~mask;
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writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
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mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
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irq_gc_unlock(gc);
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}
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@ -377,7 +412,7 @@ static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
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irq_gc_lock(gc);
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ct->mask_cache_priv |= mask;
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writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
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mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
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irq_gc_unlock(gc);
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}
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@ -390,7 +425,7 @@ static void mvebu_gpio_level_irq_mask(struct irq_data *d)
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irq_gc_lock(gc);
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ct->mask_cache_priv &= ~mask;
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writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
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mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
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irq_gc_unlock(gc);
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}
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@ -403,7 +438,7 @@ static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
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irq_gc_lock(gc);
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ct->mask_cache_priv |= mask;
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writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
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mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
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irq_gc_unlock(gc);
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}
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@ -443,8 +478,8 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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pin = d->hwirq;
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u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin);
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if (!u)
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regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &u);
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if ((u & BIT(pin)) == 0)
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return -EINVAL;
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type &= IRQ_TYPE_SENSE_MASK;
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@ -462,31 +497,30 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
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u &= ~BIT(pin);
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writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
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regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
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BIT(pin), 0);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
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u |= BIT(pin);
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writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
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regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
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BIT(pin), 1);
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break;
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case IRQ_TYPE_EDGE_BOTH: {
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u32 v;
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u32 data_in, in_pol, val;
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v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
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readl_relaxed(mvebu_gpioreg_data_in(mvchip));
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regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol);
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regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
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/*
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* set initial polarity based on current input level
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*/
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u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
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if (v & BIT(pin))
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u |= BIT(pin); /* falling */
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if ((data_in ^ in_pol) & BIT(pin))
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val = BIT(pin); /* falling */
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else
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u &= ~BIT(pin); /* rising */
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writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
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val = 0; /* raising */
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regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
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BIT(pin), val);
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break;
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||||
}
|
||||
}
|
||||
@ -497,7 +531,7 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
u32 cause, type;
|
||||
u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
|
||||
int i;
|
||||
|
||||
if (mvchip == NULL)
|
||||
@ -505,10 +539,12 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
|
||||
readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
|
||||
cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
|
||||
readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
|
||||
regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
|
||||
level_mask = mvebu_gpio_read_level_mask(mvchip);
|
||||
edge_cause = mvebu_gpio_read_edge_cause(mvchip);
|
||||
edge_mask = mvebu_gpio_read_edge_mask(mvchip);
|
||||
|
||||
cause = (data_in ^ level_mask) | (edge_cause & edge_mask);
|
||||
|
||||
for (i = 0; i < mvchip->chip.ngpio; i++) {
|
||||
int irq;
|
||||
@ -523,9 +559,9 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
|
||||
/* Swap polarity (race with GPIO line) */
|
||||
u32 polarity;
|
||||
|
||||
polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
|
||||
regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &polarity);
|
||||
polarity ^= BIT(i);
|
||||
writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
|
||||
regmap_write(mvchip->regs, GPIO_IN_POL_OFF, polarity);
|
||||
}
|
||||
|
||||
generic_handle_irq(irq);
|
||||
@ -628,7 +664,7 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
|
||||
state->period = 1;
|
||||
}
|
||||
|
||||
u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
|
||||
regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &u);
|
||||
if (u)
|
||||
state->enabled = true;
|
||||
else
|
||||
@ -691,8 +727,8 @@ static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
|
||||
{
|
||||
struct mvebu_pwm *mvpwm = mvchip->mvpwm;
|
||||
|
||||
mvpwm->blink_select =
|
||||
readl_relaxed(mvebu_gpioreg_blink_counter_select(mvchip));
|
||||
regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF,
|
||||
&mvpwm->blink_select);
|
||||
mvpwm->blink_on_duration =
|
||||
readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
|
||||
mvpwm->blink_off_duration =
|
||||
@ -703,8 +739,8 @@ static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
|
||||
{
|
||||
struct mvebu_pwm *mvpwm = mvchip->mvpwm;
|
||||
|
||||
writel_relaxed(mvpwm->blink_select,
|
||||
mvebu_gpioreg_blink_counter_select(mvchip));
|
||||
regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF,
|
||||
mvpwm->blink_select);
|
||||
writel_relaxed(mvpwm->blink_on_duration,
|
||||
mvebu_pwmreg_blink_on_duration(mvpwm));
|
||||
writel_relaxed(mvpwm->blink_off_duration,
|
||||
@ -747,7 +783,7 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
|
||||
set = U32_MAX;
|
||||
else
|
||||
return -EINVAL;
|
||||
writel_relaxed(0, mvebu_gpioreg_blink_counter_select(mvchip));
|
||||
regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF, 0);
|
||||
|
||||
mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
|
||||
if (!mvpwm)
|
||||
@ -783,14 +819,14 @@ static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
||||
u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
|
||||
int i;
|
||||
|
||||
out = readl_relaxed(mvebu_gpioreg_out(mvchip));
|
||||
io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
|
||||
blink = readl_relaxed(mvebu_gpioreg_blink(mvchip));
|
||||
in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
|
||||
data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip));
|
||||
cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip));
|
||||
edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
|
||||
lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
|
||||
regmap_read(mvchip->regs, GPIO_OUT_OFF, &out);
|
||||
regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &io_conf);
|
||||
regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &blink);
|
||||
regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol);
|
||||
regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
|
||||
cause = mvebu_gpio_read_edge_cause(mvchip);
|
||||
edg_msk = mvebu_gpio_read_edge_mask(mvchip);
|
||||
lvl_msk = mvebu_gpio_read_level_mask(mvchip);
|
||||
|
||||
for (i = 0; i < chip->ngpio; i++) {
|
||||
const char *label;
|
||||
@ -858,36 +894,36 @@ static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
|
||||
int i;
|
||||
|
||||
mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip));
|
||||
mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip));
|
||||
mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip));
|
||||
mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip));
|
||||
regmap_read(mvchip->regs, GPIO_OUT_OFF, &mvchip->out_reg);
|
||||
regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &mvchip->io_conf_reg);
|
||||
regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &mvchip->blink_en_reg);
|
||||
regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &mvchip->in_pol_reg);
|
||||
|
||||
switch (mvchip->soc_variant) {
|
||||
case MVEBU_GPIO_SOC_VARIANT_ORION:
|
||||
mvchip->edge_mask_regs[0] =
|
||||
readl(mvchip->membase + GPIO_EDGE_MASK_OFF);
|
||||
mvchip->level_mask_regs[0] =
|
||||
readl(mvchip->membase + GPIO_LEVEL_MASK_OFF);
|
||||
regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF,
|
||||
&mvchip->edge_mask_regs[0]);
|
||||
regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF,
|
||||
&mvchip->level_mask_regs[0]);
|
||||
break;
|
||||
case MVEBU_GPIO_SOC_VARIANT_MV78200:
|
||||
for (i = 0; i < 2; i++) {
|
||||
mvchip->edge_mask_regs[i] =
|
||||
readl(mvchip->membase +
|
||||
GPIO_EDGE_MASK_MV78200_OFF(i));
|
||||
mvchip->level_mask_regs[i] =
|
||||
readl(mvchip->membase +
|
||||
GPIO_LEVEL_MASK_MV78200_OFF(i));
|
||||
regmap_read(mvchip->regs,
|
||||
GPIO_EDGE_MASK_MV78200_OFF(i),
|
||||
&mvchip->edge_mask_regs[i]);
|
||||
regmap_read(mvchip->regs,
|
||||
GPIO_LEVEL_MASK_MV78200_OFF(i),
|
||||
&mvchip->level_mask_regs[i]);
|
||||
}
|
||||
break;
|
||||
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
|
||||
for (i = 0; i < 4; i++) {
|
||||
mvchip->edge_mask_regs[i] =
|
||||
readl(mvchip->membase +
|
||||
GPIO_EDGE_MASK_ARMADAXP_OFF(i));
|
||||
mvchip->level_mask_regs[i] =
|
||||
readl(mvchip->membase +
|
||||
GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
|
||||
regmap_read(mvchip->regs,
|
||||
GPIO_EDGE_MASK_ARMADAXP_OFF(i),
|
||||
&mvchip->edge_mask_regs[i]);
|
||||
regmap_read(mvchip->regs,
|
||||
GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
|
||||
&mvchip->level_mask_regs[i]);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@ -905,35 +941,36 @@ static int mvebu_gpio_resume(struct platform_device *pdev)
|
||||
struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
|
||||
int i;
|
||||
|
||||
writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip));
|
||||
writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip));
|
||||
writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip));
|
||||
writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip));
|
||||
regmap_write(mvchip->regs, GPIO_OUT_OFF, mvchip->out_reg);
|
||||
regmap_write(mvchip->regs, GPIO_IO_CONF_OFF, mvchip->io_conf_reg);
|
||||
regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF, mvchip->blink_en_reg);
|
||||
regmap_write(mvchip->regs, GPIO_IN_POL_OFF, mvchip->in_pol_reg);
|
||||
|
||||
switch (mvchip->soc_variant) {
|
||||
case MVEBU_GPIO_SOC_VARIANT_ORION:
|
||||
writel(mvchip->edge_mask_regs[0],
|
||||
mvchip->membase + GPIO_EDGE_MASK_OFF);
|
||||
writel(mvchip->level_mask_regs[0],
|
||||
mvchip->membase + GPIO_LEVEL_MASK_OFF);
|
||||
regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF,
|
||||
mvchip->edge_mask_regs[0]);
|
||||
regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF,
|
||||
mvchip->level_mask_regs[0]);
|
||||
break;
|
||||
case MVEBU_GPIO_SOC_VARIANT_MV78200:
|
||||
for (i = 0; i < 2; i++) {
|
||||
writel(mvchip->edge_mask_regs[i],
|
||||
mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i));
|
||||
writel(mvchip->level_mask_regs[i],
|
||||
mvchip->membase +
|
||||
GPIO_LEVEL_MASK_MV78200_OFF(i));
|
||||
regmap_write(mvchip->regs,
|
||||
GPIO_EDGE_MASK_MV78200_OFF(i),
|
||||
mvchip->edge_mask_regs[i]);
|
||||
regmap_write(mvchip->regs,
|
||||
GPIO_LEVEL_MASK_MV78200_OFF(i),
|
||||
mvchip->level_mask_regs[i]);
|
||||
}
|
||||
break;
|
||||
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
|
||||
for (i = 0; i < 4; i++) {
|
||||
writel(mvchip->edge_mask_regs[i],
|
||||
mvchip->membase +
|
||||
GPIO_EDGE_MASK_ARMADAXP_OFF(i));
|
||||
writel(mvchip->level_mask_regs[i],
|
||||
mvchip->membase +
|
||||
GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
|
||||
regmap_write(mvchip->regs,
|
||||
GPIO_EDGE_MASK_ARMADAXP_OFF(i),
|
||||
mvchip->edge_mask_regs[i]);
|
||||
regmap_write(mvchip->regs,
|
||||
GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
|
||||
mvchip->level_mask_regs[i]);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@ -946,6 +983,13 @@ static int mvebu_gpio_resume(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct regmap_config mvebu_gpio_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static int mvebu_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct mvebu_gpio_chip *mvchip;
|
||||
@ -954,6 +998,7 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
|
||||
struct resource *res;
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_chip_type *ct;
|
||||
void __iomem *base;
|
||||
unsigned int ngpios;
|
||||
bool have_irqs;
|
||||
int soc_variant;
|
||||
@ -1009,11 +1054,15 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
|
||||
mvchip->chip.of_node = np;
|
||||
mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
|
||||
|
||||
spin_lock_init(&mvchip->lock);
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
mvchip->membase = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mvchip->membase))
|
||||
return PTR_ERR(mvchip->membase);
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
|
||||
&mvebu_gpio_regmap_config);
|
||||
if (IS_ERR(mvchip->regs))
|
||||
return PTR_ERR(mvchip->regs);
|
||||
|
||||
/*
|
||||
* The Armada XP has a second range of registers for the
|
||||
@ -1021,10 +1070,15 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
|
||||
*/
|
||||
if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
|
||||
res);
|
||||
if (IS_ERR(mvchip->percpu_membase))
|
||||
return PTR_ERR(mvchip->percpu_membase);
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
mvchip->percpu_regs =
|
||||
devm_regmap_init_mmio(&pdev->dev, base,
|
||||
&mvebu_gpio_regmap_config);
|
||||
if (IS_ERR(mvchip->percpu_regs))
|
||||
return PTR_ERR(mvchip->percpu_regs);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1032,30 +1086,30 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
|
||||
*/
|
||||
switch (soc_variant) {
|
||||
case MVEBU_GPIO_SOC_VARIANT_ORION:
|
||||
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
|
||||
writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
|
||||
writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
|
||||
regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
|
||||
regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
|
||||
regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
|
||||
break;
|
||||
case MVEBU_GPIO_SOC_VARIANT_MV78200:
|
||||
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
|
||||
regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
|
||||
for (cpu = 0; cpu < 2; cpu++) {
|
||||
writel_relaxed(0, mvchip->membase +
|
||||
GPIO_EDGE_MASK_MV78200_OFF(cpu));
|
||||
writel_relaxed(0, mvchip->membase +
|
||||
GPIO_LEVEL_MASK_MV78200_OFF(cpu));
|
||||
regmap_write(mvchip->regs,
|
||||
GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
|
||||
regmap_write(mvchip->regs,
|
||||
GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
|
||||
}
|
||||
break;
|
||||
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
|
||||
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
|
||||
writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
|
||||
writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
|
||||
regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
|
||||
regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
|
||||
regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
|
||||
for (cpu = 0; cpu < 4; cpu++) {
|
||||
writel_relaxed(0, mvchip->percpu_membase +
|
||||
GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
|
||||
writel_relaxed(0, mvchip->percpu_membase +
|
||||
GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
|
||||
writel_relaxed(0, mvchip->percpu_membase +
|
||||
GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
|
||||
regmap_write(mvchip->percpu_regs,
|
||||
GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
|
||||
regmap_write(mvchip->percpu_regs,
|
||||
GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
|
||||
regmap_write(mvchip->percpu_regs,
|
||||
GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user