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https://github.com/edk2-porting/linux-next.git
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Staging: et131x: kill the interrupt magic define and types
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
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@ -89,72 +89,30 @@
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#define ET_PMCSR_INIT 0x38
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/*
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* structure for interrupt status reg in global address map
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* located at address 0x0018
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*/
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typedef union _INTERRUPT_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 unused5:11; /* bits 21-31 */
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u32 slv_timeout:1; /* bit 20 */
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u32 mac_stat_interrupt:1; /* bit 19 */
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u32 rxmac_interrupt:1; /* bit 18 */
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u32 txmac_interrupt:1; /* bit 17 */
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u32 phy_interrupt:1; /* bit 16 */
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u32 wake_on_lan:1; /* bit 15 */
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u32 watchdog_interrupt:1; /* bit 14 */
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u32 unused4:4; /* bits 10-13 */
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u32 rxdma_err:1; /* bit 9 */
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u32 rxdma_pkt_stat_ring_low:1; /* bit 8 */
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u32 rxdma_fb_ring1_low:1; /* bit 7 */
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u32 rxdma_fb_ring0_low:1; /* bit 6 */
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u32 rxdma_xfr_done:1; /* bit 5 */
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u32 txdma_err:1; /* bit 4 */
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u32 txdma_isr:1; /* bit 3 */
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u32 unused3:1; /* bit 2 */
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u32 unused2:1; /* bit 1 */
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u32 unused1:1; /* bit 0 */
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#else
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u32 unused1:1; /* bit 0 */
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u32 unused2:1; /* bit 1 */
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u32 unused3:1; /* bit 2 */
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u32 txdma_isr:1; /* bit 3 */
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u32 txdma_err:1; /* bit 4 */
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u32 rxdma_xfr_done:1; /* bit 5 */
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u32 rxdma_fb_ring0_low:1; /* bit 6 */
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u32 rxdma_fb_ring1_low:1; /* bit 7 */
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u32 rxdma_pkt_stat_ring_low:1; /* bit 8 */
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u32 rxdma_err:1; /* bit 9 */
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u32 unused4:4; /* bits 10-13 */
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u32 watchdog_interrupt:1; /* bit 14 */
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u32 wake_on_lan:1; /* bit 15 */
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u32 phy_interrupt:1; /* bit 16 */
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u32 txmac_interrupt:1; /* bit 17 */
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u32 rxmac_interrupt:1; /* bit 18 */
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u32 mac_stat_interrupt:1; /* bit 19 */
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u32 slv_timeout:1; /* bit 20 */
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u32 unused5:11; /* bits 21-31 */
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#endif
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} bits;
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} INTERRUPT_t, *PINTERRUPT_t;
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/*
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* structure for interrupt mask reg in global address map
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* located at address 0x001C
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* Defined earlier (INTERRUPT_t), but 'watchdog_interrupt' is not used.
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* Interrupt status reg at address 0x0018
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*/
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/*
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* structure for interrupt alias clear mask reg in global address map
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* located at address 0x0020
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* Defined earlier (INTERRUPT_t)
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*/
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#define ET_INTR_TXDMA_ISR 0x00000008
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#define ET_INTR_TXDMA_ERR 0x00000010
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#define ET_INTR_RXDMA_XFR_DONE 0x00000020
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#define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
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#define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
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#define ET_INTR_RXDMA_STAT_LOW 0x00000100
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#define ET_INTR_RXDMA_ERR 0x00000200
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#define ET_INTR_WATCHDOG 0x00004000
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#define ET_INTR_WOL 0x00008000
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#define ET_INTR_PHY 0x00010000
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#define ET_INTR_TXMAC 0x00020000
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#define ET_INTR_RXMAC 0x00040000
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#define ET_INTR_MAC_STAT 0x00080000
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#define ET_INTR_SLV_TIMEOUT 0x00100000
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/*
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* structure for interrupt status alias reg in global address map
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* located at address 0x0024
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* Defined earlier (INTERRUPT_t)
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* Interrupt mask register at address 0x001C
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* Interrupt alias clear mask reg at address 0x0020
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* Interrupt status alias reg at address 0x0024
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*
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* Same masks as above
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*/
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/*
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@ -256,10 +214,10 @@ typedef struct _GLOBAL_t { /* Location: */
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u32 rxq_end_addr; /* 0x000C */
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u32 pm_csr; /* 0x0010 */
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u32 unused; /* 0x0014 */
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INTERRUPT_t int_status; /* 0x0018 */
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INTERRUPT_t int_mask; /* 0x001C */
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INTERRUPT_t int_alias_clr_en; /* 0x0020 */
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INTERRUPT_t int_status_alias; /* 0x0024 */
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u32 int_status; /* 0x0018 */
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u32 int_mask; /* 0x001C */
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u32 int_alias_clr_en; /* 0x0020 */
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u32 int_status_alias; /* 0x0024 */
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SW_RESET_t sw_reset; /* 0x0028 */
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SLV_TIMER_t slv_timer; /* 0x002C */
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MSI_CONFIG_t msi_config; /* 0x0030 */
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@ -174,26 +174,41 @@ void ConfigMMCRegs(struct et131x_adapter *etdev)
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DBG_LEAVE(et131x_dbginfo);
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}
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/**
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* et131x_enable_interrupts - enable interrupt
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* @adapter: et131x device
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*
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* Enable the appropriate interrupts on the ET131x according to our
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* configuration
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*/
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void et131x_enable_interrupts(struct et131x_adapter *adapter)
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{
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uint32_t MaskValue;
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u32 mask;
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/* Enable all global interrupts */
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if (adapter->FlowControl == TxOnly || adapter->FlowControl == Both)
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MaskValue = INT_MASK_ENABLE;
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mask = INT_MASK_ENABLE;
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else
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MaskValue = INT_MASK_ENABLE_NO_FLOW;
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mask = INT_MASK_ENABLE_NO_FLOW;
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if (adapter->DriverNoPhyAccess)
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MaskValue |= 0x10000;
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mask |= ET_INTR_PHY;
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adapter->CachedMaskValue.value = MaskValue;
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writel(MaskValue, &adapter->regs->global.int_mask.value);
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adapter->CachedMaskValue = mask;
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writel(mask, &adapter->regs->global.int_mask);
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}
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/**
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* et131x_disable_interrupts - interrupt disable
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* @adapter: et131x device
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*
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* Block all interrupts from the et131x device at the device itself
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*/
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void et131x_disable_interrupts(struct et131x_adapter *adapter)
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{
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/* Disable all global interrupts */
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adapter->CachedMaskValue.value = INT_MASK_DISABLE;
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writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask.value);
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adapter->CachedMaskValue = INT_MASK_DISABLE;
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writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
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}
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@ -184,7 +184,7 @@ typedef struct _ce_stats_t {
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#endif /* CONFIG_ET131X_DEBUG */
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u32 SynchrounousIterations;
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INTERRUPT_t InterruptStatus;
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u32 InterruptStatus;
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} CE_STATS_t, *PCE_STATS_t;
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/* The private adapter structure */
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@ -260,7 +260,7 @@ struct et131x_adapter {
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/* Minimize init-time */
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struct timer_list ErrorTimer;
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MP_POWER_MGMT PoMgmt;
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INTERRUPT_t CachedMaskValue;
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u32 CachedMaskValue;
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/* Xcvr status at last poll */
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MI_BMSR_t Bmsr;
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@ -108,7 +108,7 @@ irqreturn_t et131x_isr(int irq, void *dev_id)
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bool handled = true;
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struct net_device *netdev = (struct net_device *)dev_id;
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struct et131x_adapter *adapter = NULL;
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INTERRUPT_t status;
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u32 status;
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if (netdev == NULL || !netif_device_present(netdev)) {
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DBG_WARNING(et131x_dbginfo,
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@ -129,17 +129,17 @@ irqreturn_t et131x_isr(int irq, void *dev_id)
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/* Get a copy of the value in the interrupt status register
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* so we can process the interrupting section
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*/
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status.value = readl(&adapter->regs->global.int_status.value);
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status = readl(&adapter->regs->global.int_status);
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if (adapter->FlowControl == TxOnly ||
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adapter->FlowControl == Both) {
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status.value &= ~INT_MASK_ENABLE;
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status &= ~INT_MASK_ENABLE;
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} else {
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status.value &= ~INT_MASK_ENABLE_NO_FLOW;
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status &= ~INT_MASK_ENABLE_NO_FLOW;
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}
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/* Make sure this is our interrupt */
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if (!status.value) {
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if (!status) {
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#ifdef CONFIG_ET131X_DEBUG
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adapter->Stats.UnhandledInterruptsPerSec++;
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#endif
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@ -151,32 +151,32 @@ irqreturn_t et131x_isr(int irq, void *dev_id)
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/* This is our interrupt, so process accordingly */
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#ifdef CONFIG_ET131X_DEBUG
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if (status.bits.rxdma_xfr_done)
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if (status & ET_INTR_RXDMA_XFR_DONE)
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adapter->Stats.RxDmaInterruptsPerSec++;
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if (status.bits.txdma_isr)
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if (status & ET_INTR_TXDMA_ISR)
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adapter->Stats.TxDmaInterruptsPerSec++;
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#endif
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if (status.bits.watchdog_interrupt) {
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if (status & ET_INTR_WATCHDOG) {
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PMP_TCB pMpTcb = adapter->TxRing.CurrSendHead;
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if (pMpTcb)
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if (++pMpTcb->PacketStaleCount > 1)
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status.bits.txdma_isr = 1;
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status |= ET_INTR_TXDMA_ISR;
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if (adapter->RxRing.UnfinishedReceives)
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status.bits.rxdma_xfr_done = 1;
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status |= ET_INTR_RXDMA_XFR_DONE;
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else if (pMpTcb == NULL)
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writel(0, &adapter->regs->global.watchdog_timer);
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status.bits.watchdog_interrupt = 0;
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status &= ~ET_INTR_WATCHDOG;
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#ifdef CONFIG_ET131X_DEBUG
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adapter->Stats.WatchDogInterruptsPerSec++;
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#endif
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}
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if (status.value == 0) {
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if (status == 0) {
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/* This interrupt has in some way been "handled" by
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* the ISR. Either it was a spurious Rx interrupt, or
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* it was a Tx interrupt that has been filtered by
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@ -213,7 +213,7 @@ void et131x_isr_handler(struct work_struct *work)
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{
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struct et131x_adapter *etdev =
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container_of(work, struct et131x_adapter, task);
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INTERRUPT_t GlobStatus = etdev->Stats.InterruptStatus;
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u32 status = etdev->Stats.InterruptStatus;
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ADDRESS_MAP_t __iomem *iomem = etdev->regs;
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/*
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@ -222,22 +222,22 @@ void et131x_isr_handler(struct work_struct *work)
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* exit.
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*/
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/* Handle all the completed Transmit interrupts */
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if (GlobStatus.bits.txdma_isr) {
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if (status & ET_INTR_TXDMA_ISR) {
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DBG_TX(et131x_dbginfo, "TXDMA_ISR interrupt\n");
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et131x_handle_send_interrupt(etdev);
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}
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/* Handle all the completed Receives interrupts */
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if (GlobStatus.bits.rxdma_xfr_done) {
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if (status & ET_INTR_RXDMA_XFR_DONE) {
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DBG_RX(et131x_dbginfo, "RXDMA_XFR_DONE interrupt\n");
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et131x_handle_recv_interrupt(etdev);
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}
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GlobStatus.value &= 0xffffffd7;
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status &= 0xffffffd7;
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if (GlobStatus.value) {
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if (status) {
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/* Handle the TXDMA Error interrupt */
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if (GlobStatus.bits.txdma_err) {
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if (status & ET_INTR_TXDMA_ERR) {
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TXDMA_ERROR_t TxDmaErr;
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/* Following read also clears the register (COR) */
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@ -249,8 +249,7 @@ void et131x_isr_handler(struct work_struct *work)
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}
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/* Handle Free Buffer Ring 0 and 1 Low interrupt */
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if (GlobStatus.bits.rxdma_fb_ring0_low ||
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GlobStatus.bits.rxdma_fb_ring1_low) {
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if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
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/*
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* This indicates the number of unused buffers in
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* RXDMA free buffer ring 0 is <= the limit you
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@ -292,7 +291,7 @@ void et131x_isr_handler(struct work_struct *work)
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}
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/* Handle Packet Status Ring Low Interrupt */
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if (GlobStatus.bits.rxdma_pkt_stat_ring_low) {
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if (status & ET_INTR_RXDMA_STAT_LOW) {
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DBG_WARNING(et131x_dbginfo,
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"RXDMA_PKT_STAT_RING_LOW interrupt\n");
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@ -308,7 +307,7 @@ void et131x_isr_handler(struct work_struct *work)
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}
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/* Handle RXDMA Error Interrupt */
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if (GlobStatus.bits.rxdma_err) {
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if (status & ET_INTR_RXDMA_ERR) {
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/*
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* The rxdma_error interrupt is sent when a time-out
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* on a request issued by the JAGCore has occurred or
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@ -337,7 +336,7 @@ void et131x_isr_handler(struct work_struct *work)
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}
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/* Handle the Wake on LAN Event */
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if (GlobStatus.bits.wake_on_lan) {
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if (status & ET_INTR_WOL) {
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/*
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* This is a secondary interrupt for wake on LAN.
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* The driver should never see this, if it does,
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@ -349,7 +348,7 @@ void et131x_isr_handler(struct work_struct *work)
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}
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/* Handle the PHY interrupt */
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if (GlobStatus.bits.phy_interrupt) {
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if (status & ET_INTR_PHY) {
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u32 pm_csr;
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MI_BMSR_t BmsrInts, BmsrData;
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MI_ISR_t myIsr;
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@ -398,7 +397,7 @@ void et131x_isr_handler(struct work_struct *work)
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}
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/* Let's move on to the TxMac */
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if (GlobStatus.bits.txmac_interrupt) {
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if (status & ET_INTR_TXMAC) {
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etdev->TxRing.TxMacErr.value =
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readl(&iomem->txmac.err.value);
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@ -424,7 +423,7 @@ void et131x_isr_handler(struct work_struct *work)
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}
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/* Handle RXMAC Interrupt */
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if (GlobStatus.bits.rxmac_interrupt) {
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if (status & ET_INTR_RXMAC) {
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/*
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* These interrupts are catastrophic to the device,
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* what we need to do is disable the interrupts and
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@ -452,7 +451,7 @@ void et131x_isr_handler(struct work_struct *work)
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}
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/* Handle MAC_STAT Interrupt */
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if (GlobStatus.bits.mac_stat_interrupt) {
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if (status & ET_INTR_MAC_STAT) {
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/*
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* This means at least one of the un-masked counters
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* in the MAC_STAT block has rolled over. Use this
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@ -464,7 +463,7 @@ void et131x_isr_handler(struct work_struct *work)
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}
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/* Handle SLV Timeout Interrupt */
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if (GlobStatus.bits.slv_timeout) {
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if (status & ET_INTR_SLV_TIMEOUT) {
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/*
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* This means a timeout has occured on a read or
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* write request to one of the JAGCore registers. The
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