renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-18 18:23:53 +08:00
Code

Merge tag 'sti-dt-for-v3.16-1' of git://git.stlinux.com/devel/kernel/linux-sti into next/dt

Browse Source 
Merge "ARM: STi: DT changes for v3.16, v3" from Maxime Coquelin:

Please consider these STi DT updates for v3.16.

This 3rd version takes into account Olof's comments on the v2:
        - Fix upper-cases in labels and node names
        - Sort compatibles order from specific to generic
        - Sort dts entries in Makefile

It also adds support for the B2020 revision E board for STiH416 SoC.

Note that two reset patches are part of this pull request, in order to avoid
compilation breakage.
Adding these two patches in this pull request has been accepted by Philipp Zabel.

* tag 'sti-dt-for-v3.16-1' of git://git.stlinux.com/devel/kernel/linux-sti: (23 commits)
  ARM: sti: stih41x: Provide a proper header for this DTSI file
  ARM: sti: stih416: Enable board LED support for B2020 RevE
  ARM: sti: stih416: Add support for B2020 RevE
  ARM: STi: DT: STiH41x Add clk_ignore_unused to bootargs
  ARM: STi: DT: STiH415: 415 DT Entry for clockgen A9
  ARM: STi: DT: STiH415: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed clocks
  ARM: STi: DT: STiH415: Remove unused CLK_S_ICN_REG_0 fixed clock
  ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12
  ARM: STi: DT: STiH416: 416 DT Entry for clockgen A9/DDR/GPU
  ARM: STi: DT: STiH416: 416 DT Entry for clockgen B/C/D/E/F
  ARM: STi: DT: STiH416: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed clocks
  ARM: STi: DT: STiH416: Remove unused CLK_S_ICN_REG_0 fixed clock
  ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12
  ARM: STi: DT: STiH41x: Rename CLK_SYSIN into clk_sysin
  ARM: STi: DT: add keyscan for stih41x-b2000
  ARM: STi: DT: add keyscan for stih416
  ARM: STi: DT: add keyscan for stih415
  driver: reset: sti: add keyscan for stih416
  driver: reset: sti: add keyscan for stih415
  ARM: dts: STiH407: Add B2120 board support
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-05-23 22:35:56 +02:00
commit 21c27cabe6
25 changed files with 2402 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/boot/dts/Makefile
View File

@ -336,10 +336,12 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear320-evb.dtb \
spear320-hmi.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
stih416-b2000.dtb \
dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
stih415-b2000.dtb \
stih415-b2020.dtb \
stih416-b2020.dtb
stih416-b2000.dtb \
stih416-b2020.dtb \
stih416-b2020-revE.dtb
dtb-$(CONFIG_ARCH_SUNXI) += \
sun4i-a10-a1000.dtb \
sun4i-a10-cubieboard.dtb \

78
arch/arm/boot/dts/stih407-b2120.dts Normal file
View File

@ -0,0 +1,78 @@
/*
* Copyright (C) 2014 STMicroelectronics (R&D) Limited.
* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "stih407.dtsi"
/ {
model = "STiH407 B2120";
compatible = "st,stih407-b2120", "st,stih407";
chosen {
bootargs = "console=ttyAS0,115200";
linux,stdout-path = &sbc_serial0;
};
memory {
device_type = "memory";
reg = <0x40000000 0x80000000>;
};
aliases {
ttyAS0 = &sbc_serial0;
};
soc {
sbc_serial0: serial@9530000 {
status = "okay";
};
leds {
compatible = "gpio-leds";
red {
#gpio-cells = <2>;
label = "Front Panel LED";
gpios = <&pio4 1 0>;
linux,default-trigger = "heartbeat";
};
green {
#gpio-cells = <2>;
gpios = <&pio1 3 0>;
default-state = "off";
};
};
i2c@9842000 {
status = "okay";
};
i2c@9843000 {
status = "okay";
};
i2c@9844000 {
status = "okay";
};
i2c@9845000 {
status = "okay";
};
i2c@9540000 {
status = "okay";
};
/* SSC11 to HDMI */
i2c@9541000 {
status = "okay";
/* HDMI V1.3a supports Standard mode only */
clock-frequency = <100000>;
st,i2c-min-scl-pulse-width-us = <0>;
st,i2c-min-sda-pulse-width-us = <5>;
};
};
};

39
arch/arm/boot/dts/stih407-clock.dtsi Normal file
View File

@ -0,0 +1,39 @@
/*
* Copyright (C) 2014 STMicroelectronics R&D Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
clocks {
/*
* Fixed 30MHz oscillator inputs to SoC
*/
clk_sysin: clk-sysin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <30000000>;
};
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: arm-periph-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <600000000>;
};
/*
* Bootloader initialized system infrastructure clock for
* serial devices.
*/
clk_ext2f_a9: clockgen-c0@13 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
clock-output-names = "clk-s-icn-reg-0";
};
};
};

615
arch/arm/boot/dts/stih407-pinctrl.dtsi Normal file
View File

@ -0,0 +1,615 @@
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "st-pincfg.h"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
aliases {
/* 0-5: PIO_SBC */
gpio0 = &pio0;
gpio1 = &pio1;
gpio2 = &pio2;
gpio3 = &pio3;
gpio4 = &pio4;
gpio5 = &pio5;
/* 10-19: PIO_FRONT0 */
gpio6 = &pio10;
gpio7 = &pio11;
gpio8 = &pio12;
gpio9 = &pio13;
gpio10 = &pio14;
gpio11 = &pio15;
gpio12 = &pio16;
gpio13 = &pio17;
gpio14 = &pio18;
gpio15 = &pio19;
/* 20: PIO_FRONT1 */
gpio16 = &pio20;
/* 30-35: PIO_REAR */
gpio17 = &pio30;
gpio18 = &pio31;
gpio19 = &pio32;
gpio20 = &pio33;
gpio21 = &pio34;
gpio22 = &pio35;
/* 40-42: PIO_FLASH */
gpio23 = &pio40;
gpio24 = &pio41;
gpio25 = &pio42;
};
soc {
pin-controller-sbc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-sbc-pinctrl";
st,syscfg = <&syscfg_sbc>;
reg = <0x0961f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
interrupts-names = "irqmux";
ranges = <0 0x09610000 0x6000>;
pio0: gpio@09610000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x100>;
st,bank-name = "PIO0";
};
pio1: gpio@09611000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO1";
};
pio2: gpio@09612000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO2";
};
pio3: gpio@09613000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO3";
};
pio4: gpio@09614000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO4";
};
pio5: gpio@09615000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x100>;
st,bank-name = "PIO5";
};
rc {
pinctrl_ir: ir0 {
st,pins {
ir = <&pio4 0 ALT2 IN>;
};
};
};
/* SBC_ASC0 - UART10 */
sbc_serial0 {
pinctrl_sbc_serial0: sbc_serial0-0 {
st,pins {
tx = <&pio3 4 ALT1 OUT>;
rx = <&pio3 5 ALT1 IN>;
};
};
};
/* SBC_ASC1 - UART11 */
sbc_serial1 {
pinctrl_sbc_serial1: sbc_serial1-0 {
st,pins {
tx = <&pio2 6 ALT3 OUT>;
rx = <&pio2 7 ALT3 IN>;
};
};
};
i2c10 {
pinctrl_i2c10_default: i2c10-default {
st,pins {
sda = <&pio4 6 ALT1 BIDIR>;
scl = <&pio4 5 ALT1 BIDIR>;
};
};
};
i2c11 {
pinctrl_i2c11_default: i2c11-default {
st,pins {
sda = <&pio5 1 ALT1 BIDIR>;
scl = <&pio5 0 ALT1 BIDIR>;
};
};
};
keyscan {
pinctrl_keyscan: keyscan {
st,pins {
keyin0 = <&pio4 0 ALT6 IN>;
keyin1 = <&pio4 5 ALT4 IN>;
keyin2 = <&pio0 4 ALT2 IN>;
keyin3 = <&pio2 6 ALT2 IN>;
keyout0 = <&pio4 6 ALT4 OUT>;
keyout1 = <&pio1 7 ALT2 OUT>;
keyout2 = <&pio0 6 ALT2 OUT>;
keyout3 = <&pio2 7 ALT2 OUT>;
};
};
};
gmac1 {
/*
* Almost all the boards based on STiH407 SoC have an embedded
* switch where the mdio/mdc have been used for managing the SMI
* iface via I2C. For this reason these lines can be allocated
* by using dedicated configuration (in case of there will be a
* standard PHY transceiver on-board).
*/
pinctrl_rgmii1: rgmii1-0 {
st,pins {
txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>;
clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>;
};
};
pinctrl_rgmii1_mdio: rgmii1-mdio {
st,pins {
mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
mdint = <&pio1 3 ALT1 IN BYPASS 0>;
};
};
pinctrl_mii1: mii1 {
st,pins {
txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
col = <&pio0 7 ALT1 IN BYPASS 1000>;
mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
crs = <&pio1 2 ALT1 IN BYPASS 1000>;
mdint = <&pio1 3 ALT1 IN BYPASS 0>;
rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
};
};
};
pwm1 {
pinctrl_pwm1_chan0_default: pwm1-0-default {
st,pins {
pwm-out = <&pio3 0 ALT1 OUT>;
};
};
pinctrl_pwm1_chan1_default: pwm1-1-default {
st,pins {
pwm-out = <&pio4 4 ALT1 OUT>;
};
};
pinctrl_pwm1_chan2_default: pwm1-2-default {
st,pins {
pwm-out = <&pio4 6 ALT3 OUT>;
};
};
pinctrl_pwm1_chan3_default: pwm1-3-default {
st,pins {
pwm-out = <&pio4 7 ALT3 OUT>;
};
};
};
};
pin-controller-front0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-front-pinctrl";
st,syscfg = <&syscfg_front>;
reg = <0x0920f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
interrupts-names = "irqmux";
ranges = <0 0x09200000 0x10000>;
pio10: pio@09200000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x100>;
st,bank-name = "PIO10";
};
pio11: pio@09201000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO11";
};
pio12: pio@09202000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO12";
};
pio13: pio@09203000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO13";
};
pio14: pio@09204000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO14";
};
pio15: pio@09205000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x100>;
st,bank-name = "PIO15";
};
pio16: pio@09206000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x100>;
st,bank-name = "PIO16";
};
pio17: pio@09207000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x100>;
st,bank-name = "PIO17";
};
pio18: pio@09208000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x100>;
st,bank-name = "PIO18";
};
pio19: pio@09209000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x9000 0x100>;
st,bank-name = "PIO19";
};
/* Comms */
serial0 {
pinctrl_serial0: serial0-0 {
st,pins {
tx = <&pio17 0 ALT1 OUT>;
rx = <&pio17 1 ALT1 IN>;
};
};
};
serial1 {
pinctrl_serial1: serial1-0 {
st,pins {
tx = <&pio16 0 ALT1 OUT>;
rx = <&pio16 1 ALT1 IN>;
};
};
};
serial2 {
pinctrl_serial2: serial2-0 {
st,pins {
tx = <&pio15 0 ALT1 OUT>;
rx = <&pio15 1 ALT1 IN>;
};
};
};
mmc1 {
pinctrl_sd1: sd1-0 {
st,pins {
sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
sd_led = <&pio16 6 ALT6 OUT>;
sd_pwren = <&pio16 7 ALT6 OUT>;
sd_cd = <&pio19 0 ALT6 IN>;
sd_wp = <&pio19 1 ALT6 IN>;
};
};
};
i2c0 {
pinctrl_i2c0_default: i2c0-default {
st,pins {
sda = <&pio10 6 ALT2 BIDIR>;
scl = <&pio10 5 ALT2 BIDIR>;
};
};
};
i2c1 {
pinctrl_i2c1_default: i2c1-default {
st,pins {
sda = <&pio11 1 ALT2 BIDIR>;
scl = <&pio11 0 ALT2 BIDIR>;
};
};
};
i2c2 {
pinctrl_i2c2_default: i2c2-default {
st,pins {
sda = <&pio15 6 ALT2 BIDIR>;
scl = <&pio15 5 ALT2 BIDIR>;
};
};
};
i2c3 {
pinctrl_i2c3_default: i2c3-default {
st,pins {
sda = <&pio18 6 ALT1 BIDIR>;
scl = <&pio18 5 ALT1 BIDIR>;
};
};
};
spi0 {
pinctrl_spi0_default: spi0-default {
st,pins {
mtsr = <&pio12 6 ALT2 BIDIR>;
mrst = <&pio12 7 ALT2 BIDIR>;
scl = <&pio12 5 ALT2 BIDIR>;
};
};
};
};
pin-controller-front1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-front-pinctrl";
st,syscfg = <&syscfg_front>;
reg = <0x0921f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
interrupts-names = "irqmux";
ranges = <0 0x09210000 0x10000>;
pio20: pio@09210000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x100>;
st,bank-name = "PIO20";
};
};
pin-controller-rear {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-rear-pinctrl";
st,syscfg = <&syscfg_rear>;
reg = <0x0922f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
interrupts-names = "irqmux";
ranges = <0 0x09220000 0x6000>;
pio30: gpio@09220000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x100>;
st,bank-name = "PIO30";
};
pio31: gpio@09221000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO31";
};
pio32: gpio@09222000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO32";
};
pio33: gpio@09223000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO33";
};
pio34: gpio@09224000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO34";
};
pio35: gpio@09225000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x100>;
st,bank-name = "PIO35";
};
i2c4 {
pinctrl_i2c4_default: i2c4-default {
st,pins {
sda = <&pio30 1 ALT1 BIDIR>;
scl = <&pio30 0 ALT1 BIDIR>;
};
};
};
i2c5 {
pinctrl_i2c5_default: i2c5-default {
st,pins {
sda = <&pio34 4 ALT1 BIDIR>;
scl = <&pio34 3 ALT1 BIDIR>;
};
};
};
usb3 {
pinctrl_usb3: usb3-2 {
st,pins {
usb-oc-detect = <&pio35 4 ALT1 IN>;
usb-pwr-enable = <&pio35 5 ALT1 OUT>;
usb-vbus-valid = <&pio35 6 ALT1 IN>;
};
};
};
pwm0 {
pinctrl_pwm0_chan0_default: pwm0-0-default {
st,pins {
pwm-out = <&pio31 1 ALT1 OUT>;
};
};
};
};
pin-controller-flash {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-flash-pinctrl";
st,syscfg = <&syscfg_flash>;
reg = <0x0923f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
interrupts-names = "irqmux";
ranges = <0 0x09230000 0x3000>;
pio40: gpio@09230000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO40";
};
pio41: gpio@09231000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO41";
};
pio42: gpio@09232000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO42";
};
mmc0 {
pinctrl_mmc0: mmc0-0 {
st,pins {
emmc_clk = <&pio40 6 ALT1 BIDIR>;
emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
};
};
};
};
};
};

263
arch/arm/boot/dts/stih407.dtsi Normal file
View File

@ -0,0 +1,263 @@
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "stih407-clock.dtsi"
#include "stih407-pinctrl.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
intc: interrupt-controller@08761000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x08761000 0x1000>, <0x08760100 0x100>;
};
scu@08760000 {
compatible = "arm,cortex-a9-scu";
reg = <0x08760000 0x1000>;
};
timer@08760200 {
interrupt-parent = <&intc>;
compatible = "arm,cortex-a9-global-timer";
reg = <0x08760200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&arm_periph_clk>;
};
l2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0x08762000 0x1000>;
arm,data-latency = <3 3 3>;
arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
compatible = "simple-bus";
syscfg_sbc: sbc-syscfg@9620000 {
compatible = "st,stih407-sbc-syscfg", "syscon";
reg = <0x9620000 0x1000>;
};
syscfg_front: front-syscfg@9280000 {
compatible = "st,stih407-front-syscfg", "syscon";
reg = <0x9280000 0x1000>;
};
syscfg_rear: rear-syscfg@9290000 {
compatible = "st,stih407-rear-syscfg", "syscon";
reg = <0x9290000 0x1000>;
};
syscfg_flash: flash-syscfg@92a0000 {
compatible = "st,stih407-flash-syscfg", "syscon";
reg = <0x92a0000 0x1000>;
};
syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
compatible = "st,stih407-sbc-reg-syscfg", "syscon";
reg = <0x9600000 0x1000>;
};
syscfg_core: core-syscfg@92b0000 {
compatible = "st,stih407-core-syscfg", "syscon";
reg = <0x92b0000 0x1000>;
};
syscfg_lpm: lpm-syscfg@94b5100 {
compatible = "st,stih407-lpm-syscfg", "syscon";
reg = <0x94b5100 0x1000>;
};
serial@9830000 {
compatible = "st,asc";
reg = <0x9830000 0x2c>;
interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial0>;
clocks = <&clk_ext2f_a9>;
status = "disabled";
};
serial@9831000 {
compatible = "st,asc";
reg = <0x9831000 0x2c>;
interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial1>;
clocks = <&clk_ext2f_a9>;
status = "disabled";
};
serial@9832000 {
compatible = "st,asc";
reg = <0x9832000 0x2c>;
interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2>;
clocks = <&clk_ext2f_a9>;
status = "disabled";
};
/* SBC_ASC0 - UART10 */
sbc_serial0: serial@9530000 {
compatible = "st,asc";
reg = <0x9530000 0x2c>;
interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial0>;
clocks = <&clk_sysin>;
status = "disabled";
};
serial@9531000 {
compatible = "st,asc";
reg = <0x9531000 0x2c>;
interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
clocks = <&clk_sysin>;
status = "disabled";
};
i2c@9840000 {
compatible = "st,comms-ssc4-i2c";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x9840000 0x110>;
clocks = <&clk_ext2f_a9>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_default>;
status = "disabled";
};
i2c@9841000 {
compatible = "st,comms-ssc4-i2c";
reg = <0x9841000 0x110>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_ext2f_a9>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "disabled";
};
i2c@9842000 {
compatible = "st,comms-ssc4-i2c";
reg = <0x9842000 0x110>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_ext2f_a9>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_default>;
status = "disabled";
};
i2c@9843000 {
compatible = "st,comms-ssc4-i2c";
reg = <0x9843000 0x110>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_ext2f_a9>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_default>;
status = "disabled";
};
i2c@9844000 {
compatible = "st,comms-ssc4-i2c";
reg = <0x9844000 0x110>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_ext2f_a9>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_default>;
status = "disabled";
};
i2c@9845000 {
compatible = "st,comms-ssc4-i2c";
reg = <0x9845000 0x110>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_ext2f_a9>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
status = "disabled";
};
/* SSCs on SBC */
i2c@9540000 {
compatible = "st,comms-ssc4-i2c";
reg = <0x9540000 0x110>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_sysin>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c10_default>;
status = "disabled";
};
i2c@9541000 {
compatible = "st,comms-ssc4-i2c";
reg = <0x9541000 0x110>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_sysin>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c11_default>;
status = "disabled";
};
};
};

2
arch/arm/boot/dts/stih415-b2000.dts
View File

@ -11,5 +11,5 @@
#include "stih41x-b2000.dtsi"
/ {
model = "STiH415 B2000 Board";
compatible = "st,stih415", "st,stih415-b2000";
compatible = "st,stih415-b2000", "st,stih415";
};

2
arch/arm/boot/dts/stih415-b2020.dts
View File

@ -11,5 +11,5 @@
#include "stih41x-b2020.dtsi"
/ {
model = "STiH415 B2020 Board";
compatible = "st,stih415", "st,stih415-b2020";
compatible = "st,stih415-b2020", "st,stih415";
};

523
arch/arm/boot/dts/stih415-clock.dtsi
View File

@ -5,48 +5,529 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/stih415-clks.h>
/ {
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* Fixed 30MHz oscillator input to SoC
*/
CLK_SYSIN: CLK_SYSIN {
clk_sysin: clk-sysin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <30000000>;
};
/*
* ARM Peripheral clock for timers
* ClockGenAs on SASG1
*/
arm_periph_clk: arm_periph_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <500000000>;
clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>;
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll0-hs",
"clk-s-a0-pll0-ls",
"clk-s-a0-pll1";
};
clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-osc-prediv";
};
clk_s_a0_hs: clk-s-a0-hs {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
clocks = <&clk_s_a0_osc_prediv>,
<&clk_s_a0_pll 0>, /* PLL0 HS */
<&clk_s_a0_pll 2>; /* PLL1 */
clock-output-names = "clk-s-fdma-0",
"clk-s-fdma-1",
""; /* clk-s-jit-sense */
/* Fourth output unused */
};
clk_s_a0_ls: clk-s-a0-ls {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-ls",
"st,clkgena-divmux";
clocks = <&clk_s_a0_osc_prediv>,
<&clk_s_a0_pll 1>, /* PLL0 LS */
<&clk_s_a0_pll 2>; /* PLL1 */
clock-output-names = "clk-s-icn-reg-0",
"clk-s-icn-if-0",
"clk-s-icn-reg-lp-0",
"clk-s-emiss",
"clk-s-eth1-phy",
"clk-s-mii-ref-out";
/* Remaining outputs unused */
};
};
clockgen-a@fee81000 {
reg = <0xfee81000 0xb48>;
clk_s_a1_pll: clk-s-a1-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a1-pll0-hs",
"clk-s-a1-pll0-ls",
"clk-s-a1-pll1";
};
clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a1-osc-prediv";
};
clk_s_a1_hs: clk-s-a1-hs {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
clocks = <&clk_s_a1_osc_prediv>,
<&clk_s_a1_pll 0>, /* PLL0 HS */
<&clk_s_a1_pll 2>; /* PLL1 */
clock-output-names = "", /* Reserved */
"", /* Reserved */
"clk-s-stac-phy",
"clk-s-vtac-tx-phy";
};
clk_s_a1_ls: clk-s-a1-ls {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-ls",
"st,clkgena-divmux";
clocks = <&clk_s_a1_osc_prediv>,
<&clk_s_a1_pll 1>, /* PLL0 LS */
<&clk_s_a1_pll 2>; /* PLL1 */
clock-output-names = "clk-s-icn-if-2",
"clk-s-card-mmc",
"clk-s-icn-if-1",
"clk-s-gmac0-phy",
"clk-s-nand-ctrl",
"", /* Reserved */
"clk-s-mii0-ref-out",
""; /* clk-s-stac-sys */
/* Remaining outputs unused */
};
};
/*
* Bootloader initialized system infrastructure clock for
* serial devices.
* ClockGenAs on MPE41
*/
CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clockgen-a@fde12000 {
reg = <0xfde12000 0xb50>;
clk_m_a0_pll0: clk-m-a0-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a0-pll0-phi0",
"clk-m-a0-pll0-phi1",
"clk-m-a0-pll0-phi2",
"clk-m-a0-pll0-phi3";
};
clk_m_a0_pll1: clk-m-a0-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a0-pll1-phi0",
"clk-m-a0-pll1-phi1",
"clk-m-a0-pll1-phi2",
"clk-m-a0-pll1-phi3";
};
clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a0-osc-prediv";
};
clk_m_a0_div0: clk-m-a0-div0 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf0",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
<&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
clock-output-names = "clk-m-apb-pm", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"clk-m-pp-dmu-0",
"clk-m-pp-dmu-1",
"clk-m-icm-disp",
""; /* Unused */
};
clk_m_a0_div1: clk-m-a0-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "", /* Unused */
"", /* Unused */
"clk-m-a9-ext2f",
"clk-m-st40rt",
"clk-m-st231-dmu-0",
"clk-m-st231-dmu-1",
"clk-m-st231-aud",
"clk-m-st231-gp-0";
};
clk_m_a0_div2: clk-m-a0-div2 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf2",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
<&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
clock-output-names = "clk-m-st231-gp-1",
"clk-m-icn-cpu",
"clk-m-icn-stac",
"clk-m-icn-dmu-0",
"clk-m-icn-dmu-1",
"", /* Unused */
"", /* Unused */
""; /* Unused */
};
clk_m_a0_div3: clk-m-a0-div3 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf3",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
<&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
clock-output-names = "", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"clk-m-icn-eram",
"clk-m-a9-trace";
};
};
CLKS_GMAC0_PHY: clockgenA1@7 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "CLKS_GMAC0_PHY";
clockgen-a@fd6db000 {
reg = <0xfd6db000 0xb50>;
clk_m_a1_pll0: clk-m-a1-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a1-pll0-phi0",
"clk-m-a1-pll0-phi1",
"clk-m-a1-pll0-phi2",
"clk-m-a1-pll0-phi3";
};
clk_m_a1_pll1: clk-m-a1-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a1-pll1-phi0",
"clk-m-a1-pll1-phi1",
"clk-m-a1-pll1-phi2",
"clk-m-a1-pll1-phi3";
};
clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a1-osc-prediv";
};
clk_m_a1_div0: clk-m-a1-div0 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf0",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
<&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
clock-output-names = "clk-m-fdma-12",
"clk-m-fdma-10",
"clk-m-fdma-11",
"clk-m-hva-lmi",
"clk-m-proc-sc",
"clk-m-tp",
"clk-m-icn-gpu",
"clk-m-icn-vdp-0";
};
clk_m_a1_div1: clk-m-a1-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "clk-m-icn-vdp-1",
"clk-m-icn-vdp-2",
"clk-m-icn-vdp-3",
"clk-m-prv-t1-bus",
"clk-m-icn-vdp-4",
"clk-m-icn-reg-10",
"", /* Unused */
""; /* clk-m-icn-st231 */
};
clk_m_a1_div2: clk-m-a1-div2 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf2",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
<&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
clock-output-names = "clk-m-fvdp-proc-alt",
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
""; /* Unused */
};
clk_m_a1_div3: clk-m-a1-div3 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf3",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
<&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
clock-output-names = "", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
""; /* Unused */
};
};
CLKS_ETH1_PHY: clockgenA0@7 {
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "CLKS_ETH1_PHY";
compatible = "fixed-factor-clock";
clocks = <&clk_m_a0_div1 2>;
clock-div = <2>;
clock-mult = <1>;
};
clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>;
clk_m_a2_pll0: clk-m-a2-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-pll0-phi0",
"clk-m-a2-pll0-phi1",
"clk-m-a2-pll0-phi2",
"clk-m-a2-pll0-phi3";
};
clk_m_a2_pll1: clk-m-a2-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-pll1-phi0",
"clk-m-a2-pll1-phi1",
"clk-m-a2-pll1-phi2",
"clk-m-a2-pll1-phi3";
};
clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-osc-prediv";
};
clk_m_a2_div0: clk-m-a2-div0 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf0",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
<&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
clock-output-names = "clk-m-vtac-main-phy",
"clk-m-vtac-aux-phy",
"clk-m-stac-phy",
"clk-m-stac-sys",
"", /* clk-m-mpestac-pg */
"", /* clk-m-mpestac-wc */
"", /* clk-m-mpevtacaux-pg*/
""; /* clk-m-mpevtacmain-pg*/
};
clk_m_a2_div1: clk-m-a2-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "", /* clk-m-mpevtacrx0-wc */
"", /* clk-m-mpevtacrx1-wc */
"clk-m-compo-main",
"clk-m-compo-aux",
"clk-m-bdisp-0",
"clk-m-bdisp-1",
"clk-m-icn-bdisp-0",
"clk-m-icn-bdisp-1";
};
clk_m_a2_div2: clk-m-a2-div2 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf2",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
<&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
clock-output-names = "", /* clk-m-icn-hqvdp0 */
"", /* clk-m-icn-hqvdp1 */
"clk-m-icn-compo",
"", /* clk-m-icn-vdpaux */
"clk-m-icn-ts",
"clk-m-icn-reg-lp-10",
"clk-m-dcephy-impctrl",
""; /* Unused */
};
clk_m_a2_div3: clk-m-a2-div3 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf3",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
<&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
clock-output-names = ""; /* Unused */
/* Remaining outputs unused */
};
};
/*
* A9 PLL
*/
clockgen-a9@fdde00d8 {
reg = <0xfdde00d8 0x70>;
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clockgen-a9-pll-odf";
};
};
/*
* ARM CPU related clocks
*/
clk_m_a9: clk-m-a9@fdde00d8 {
#clock-cells = <0>;
compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux";
reg = <0xfdde00d8 0x4>;
clocks = <&clockgen_a9_pll 0>,
<&clockgen_a9_pll 0>,
<&clk_m_a0_div1 2>,
<&clk_m_a9_ext2f_div2>;
};
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
};
};

16
arch/arm/boot/dts/stih415-pinctrl.dtsi
View File

@ -102,6 +102,22 @@
};
};
keyscan {
pinctrl_keyscan: keyscan {
st,pins {
keyin0 = <&PIO0 2 ALT2 IN>;
keyin1 = <&PIO0 3 ALT2 IN>;
keyin2 = <&PIO0 4 ALT2 IN>;
keyin3 = <&PIO2 6 ALT2 IN>;
keyout0 = <&PIO1 6 ALT2 OUT>;
keyout1 = <&PIO1 7 ALT2 OUT>;
keyout2 = <&PIO0 6 ALT2 OUT>;
keyout3 = <&PIO2 7 ALT2 OUT>;
};
};
};
sbc_i2c0 {
pinctrl_sbc_i2c0_default: sbc_i2c0-default {
st,pins {

30
arch/arm/boot/dts/stih415.dtsi
View File

@ -82,7 +82,7 @@
interrupts = <0 197 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2>;
clocks = <&CLKS_ICN_REG_0>;
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
};
/* SBC comms block ASCs in SASG1 */
@ -91,7 +91,7 @@
status = "disabled";
reg = <0xfe531000 0x2c>;
interrupts = <0 210 0>;
clocks = <&CLK_SYSIN>;
clocks = <&clk_sysin>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
};
@ -100,7 +100,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfed40000 0x110>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CLKS_ICN_REG_0>;
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@ -113,7 +113,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfed41000 0x110>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CLKS_ICN_REG_0>;
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@ -126,7 +126,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfe540000 0x110>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CLK_SYSIN>;
clocks = <&clk_sysin>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@ -139,7 +139,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfe541000 0x110>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CLK_SYSIN>;
clocks = <&clk_sysin>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@ -170,7 +170,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii0>;
clock-names = "stmmaceth";
clocks = <&CLKS_GMAC0_PHY>;
clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>;
};
ethernet1: dwmac@fef08000 {
@ -193,18 +193,30 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii1>;
clock-names = "stmmaceth";
clocks = <&CLKS_ETH1_PHY>;
clocks = <&clk_s_a0_ls CLK_ETH1_PHY>;
};
rc: rc@fe518000 {
compatible = "st,comms-irb";
reg = <0xfe518000 0x234>;
interrupts = <0 203 0>;
clocks = <&CLK_SYSIN>;
clocks = <&clk_sysin>;
rx-mode = "infrared";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ir>;
resets = <&softreset STIH415_IRB_SOFTRESET>;
};
keyscan: keyscan@fe4b0000 {
compatible = "st,sti-keyscan";
status = "disabled";
reg = <0xfe4b0000 0x2000>;
interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
clocks = <&clk_sysin>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_keyscan>;
resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>,
<&softreset STIH415_KEYSCAN_SOFTRESET>;
};
};
};

3
arch/arm/boot/dts/stih416-b2000.dts
View File

@ -9,8 +9,7 @@
/dts-v1/;
#include "stih416.dtsi"
#include "stih41x-b2000.dtsi"
/ {
compatible = "st,stih416", "st,stih416-b2000";
model = "STiH416 B2000";
compatible = "st,stih416-b2000", "st,stih416";
};

35
arch/arm/boot/dts/stih416-b2020-revE.dts Normal file
View File

@ -0,0 +1,35 @@
/*
* Copyright (C) 2014 STMicroelectronics (R&D) Limited.
* Author: Lee Jones <lee.jones@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/dts-v1/;
#include "stih416.dtsi"
#include "stih41x-b2020.dtsi"
/ {
model = "STiH416 B2020 REV-E";
compatible = "st,stih416-b2020", "st,stih416";
soc {
leds {
compatible = "gpio-leds";
red {
#gpio-cells = <1>;
label = "Front Panel LED";
gpios = <&PIO4 1>;
linux,default-trigger = "heartbeat";
};
green {
gpios = <&PIO1 3>;
default-state = "off";
};
};
ethernet1: dwmac@fef08000 {
snps,reset-gpio = <&PIO0 7>;
};
};
};

3
arch/arm/boot/dts/stih416-b2020.dts
View File

@ -11,6 +11,5 @@
#include "stih41x-b2020.dtsi"
/ {
model = "STiH416 B2020";
compatible = "st,stih416", "st,stih416-b2020";
compatible = "st,stih416-b2020", "st,stih416";
};

741
arch/arm/boot/dts/stih416-clock.dtsi
View File

@ -6,50 +6,751 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/stih416-clks.h>
/ {
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* Fixed 30MHz oscillator inputs to SoC
*/
CLK_SYSIN: CLK_SYSIN {
clk_sysin: clk-sysin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <30000000>;
clock-output-names = "CLK_SYSIN";
};
/*
* ClockGenAs on SASG2
*/
clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>;
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll0-hs",
"clk-s-a0-pll0-ls",
"clk-s-a0-pll1";
};
clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-osc-prediv";
};
clk_s_a0_hs: clk-s-a0-hs {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
clocks = <&clk_s_a0_osc_prediv>,
<&clk_s_a0_pll 0>, /* PLL0 HS */
<&clk_s_a0_pll 2>; /* PLL1 */
clock-output-names = "clk-s-fdma-0",
"clk-s-fdma-1",
""; /* clk-s-jit-sense */
/* Fourth output unused */
};
clk_s_a0_ls: clk-s-a0-ls {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-ls",
"st,clkgena-divmux";
clocks = <&clk_s_a0_osc_prediv>,
<&clk_s_a0_pll 1>, /* PLL0 LS */
<&clk_s_a0_pll 2>; /* PLL1 */
clock-output-names = "clk-s-icn-reg-0",
"clk-s-icn-if-0",
"clk-s-icn-reg-lp-0",
"clk-s-emiss",
"clk-s-eth1-phy",
"clk-s-mii-ref-out";
/* Remaining outputs unused */
};
};
clockgen-a@fee81000 {
reg = <0xfee81000 0xb48>;
clk_s_a1_pll: clk-s-a1-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a1-pll0-hs",
"clk-s-a1-pll0-ls",
"clk-s-a1-pll1";
};
clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a1-osc-prediv";
};
clk_s_a1_hs: clk-s-a1-hs {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
clocks = <&clk_s_a1_osc_prediv>,
<&clk_s_a1_pll 0>, /* PLL0 HS */
<&clk_s_a1_pll 2>; /* PLL1 */
clock-output-names = "", /* Reserved */
"", /* Reserved */
"clk-s-stac-phy",
"clk-s-vtac-tx-phy";
};
clk_s_a1_ls: clk-s-a1-ls {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-ls",
"st,clkgena-divmux";
clocks = <&clk_s_a1_osc_prediv>,
<&clk_s_a1_pll 1>, /* PLL0 LS */
<&clk_s_a1_pll 2>; /* PLL1 */
clock-output-names = "clk-s-icn-if-2",
"clk-s-card-mmc-0",
"clk-s-icn-if-1",
"clk-s-gmac0-phy",
"clk-s-nand-ctrl",
"", /* Reserved */
"clk-s-mii0-ref-out",
"clk-s-stac-sys",
"clk-s-card-mmc-1";
/* Remaining outputs unused */
};
};
/*
* ClockGenAs on MPE42
*/
clockgen-a@fde12000 {
reg = <0xfde12000 0xb50>;
clk_m_a0_pll0: clk-m-a0-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a0-pll0-phi0",
"clk-m-a0-pll0-phi1",
"clk-m-a0-pll0-phi2",
"clk-m-a0-pll0-phi3";
};
clk_m_a0_pll1: clk-m-a0-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a0-pll1-phi0",
"clk-m-a0-pll1-phi1",
"clk-m-a0-pll1-phi2",
"clk-m-a0-pll1-phi3";
};
clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a0-osc-prediv";
};
clk_m_a0_div0: clk-m-a0-div0 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf0",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
<&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
clock-output-names = "", /* Unused */
"", /* Unused */
"clk-m-fdma-12",
"", /* Unused */
"clk-m-pp-dmu-0",
"clk-m-pp-dmu-1",
"clk-m-icm-lmi",
"clk-m-vid-dmu-0";
};
clk_m_a0_div1: clk-m-a0-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "clk-m-vid-dmu-1",
"", /* Unused */
"clk-m-a9-ext2f",
"clk-m-st40rt",
"clk-m-st231-dmu-0",
"clk-m-st231-dmu-1",
"clk-m-st231-aud",
"clk-m-st231-gp-0";
};
clk_m_a0_div2: clk-m-a0-div2 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf2",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
<&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
clock-output-names = "clk-m-st231-gp-1",
"clk-m-icn-cpu",
"clk-m-icn-stac",
"clk-m-tx-icn-dmu-0",
"clk-m-tx-icn-dmu-1",
"clk-m-tx-icn-ts",
"clk-m-icn-vdp-0",
"clk-m-icn-vdp-1";
};
clk_m_a0_div3: clk-m-a0-div3 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf3",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
<&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
clock-output-names = "", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"clk-m-icn-vp8",
"", /* Unused */
"clk-m-icn-reg-11",
"clk-m-a9-trace";
};
};
clockgen-a@fd6db000 {
reg = <0xfd6db000 0xb50>;
clk_m_a1_pll0: clk-m-a1-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a1-pll0-phi0",
"clk-m-a1-pll0-phi1",
"clk-m-a1-pll0-phi2",
"clk-m-a1-pll0-phi3";
};
clk_m_a1_pll1: clk-m-a1-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a1-pll1-phi0",
"clk-m-a1-pll1-phi1",
"clk-m-a1-pll1-phi2",
"clk-m-a1-pll1-phi3";
};
clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a1-osc-prediv";
};
clk_m_a1_div0: clk-m-a1-div0 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf0",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
<&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
clock-output-names = "", /* Unused */
"clk-m-fdma-10",
"clk-m-fdma-11",
"clk-m-hva-alt",
"clk-m-proc-sc",
"clk-m-tp",
"clk-m-rx-icn-dmu-0",
"clk-m-rx-icn-dmu-1";
};
clk_m_a1_div1: clk-m-a1-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "clk-m-rx-icn-ts",
"clk-m-rx-icn-vdp-0",
"", /* Unused */
"clk-m-prv-t1-bus",
"clk-m-icn-reg-12",
"clk-m-icn-reg-10",
"", /* Unused */
"clk-m-icn-st231";
};
clk_m_a1_div2: clk-m-a1-div2 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf2",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
<&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
clock-output-names = "clk-m-fvdp-proc-alt",
"clk-m-icn-reg-13",
"clk-m-tx-icn-gpu",
"clk-m-rx-icn-gpu",
"", /* Unused */
"", /* Unused */
"", /* clk-m-apb-pm-12 */
""; /* Unused */
};
clk_m_a1_div3: clk-m-a1-div3 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf3",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
<&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
clock-output-names = "", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
""; /* clk-m-gpu-alt */
};
};
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a0_div1 2>;
clock-div = <2>;
clock-mult = <1>;
};
clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>;
clk_m_a2_pll0: clk-m-a2-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-pll0-phi0",
"clk-m-a2-pll0-phi1",
"clk-m-a2-pll0-phi2",
"clk-m-a2-pll0-phi3";
};
clk_m_a2_pll1: clk-m-a2-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-pll1-phi0",
"clk-m-a2-pll1-phi1",
"clk-m-a2-pll1-phi2",
"clk-m-a2-pll1-phi3";
};
clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-osc-prediv";
};
clk_m_a2_div0: clk-m-a2-div0 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf0",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
<&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
clock-output-names = "clk-m-vtac-main-phy",
"clk-m-vtac-aux-phy",
"clk-m-stac-phy",
"clk-m-stac-sys",
"", /* clk-m-mpestac-pg */
"", /* clk-m-mpestac-wc */
"", /* clk-m-mpevtacaux-pg*/
""; /* clk-m-mpevtacmain-pg*/
};
clk_m_a2_div1: clk-m-a2-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "", /* clk-m-mpevtacrx0-wc */
"", /* clk-m-mpevtacrx1-wc */
"clk-m-compo-main",
"clk-m-compo-aux",
"clk-m-bdisp-0",
"clk-m-bdisp-1",
"clk-m-icn-bdisp",
"clk-m-icn-compo";
};
clk_m_a2_div2: clk-m-a2-div2 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf2",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
<&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
clock-output-names = "clk-m-icn-vdp-2",
"", /* Unused */
"clk-m-icn-reg-14",
"clk-m-mdtp",
"clk-m-jpegdec",
"", /* Unused */
"clk-m-dcephy-impctrl",
""; /* Unused */
};
clk_m_a2_div3: clk-m-a2-div3 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf3",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
<&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
clock-output-names = "", /* Unused */
""; /* clk-m-apb-pm-11 */
/* Remaining outputs unused */
};
};
/*
* A9 PLL
*/
clockgen-a9@fdde08b0 {
reg = <0xfdde08b0 0x70>;
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clockgen-a9-pll-odf";
};
};
/*
* ARM CPU related clocks
*/
clk_m_a9: clk-m-a9@fdde08ac {
#clock-cells = <0>;
compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux";
reg = <0xfdde08ac 0x4>;
clocks = <&clockgen_a9_pll 0>,
<&clockgen_a9_pll 0>,
<&clk_m_a0_div1 2>,
<&clk_m_a9_ext2f_div2>;
};
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: arm_periph_clk {
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <600000000>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
/*
* Bootloader initialized system infrastructure clock for
* serial devices.
* Frequency synthesizers on the SASG2
*/
CLK_S_ICN_REG_0: clockgenA0@4 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-output-names = "CLK_S_ICN_REG_0";
clockgen_b0: clockgen-b0@fee108b4 {
#clock-cells = <1>;
compatible = "st,stih416-quadfs216", "st,quadfs";
reg = <0xfee108b4 0x44>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-usb48",
"clk-s-dss",
"clk-s-stfe-frc-2",
"clk-s-thsens-scard";
};
CLK_S_GMAC0_PHY: clockgenA1@7 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "CLK_S_GMAC0_PHY";
clockgen_b1: clockgen-b1@fe8308c4 {
#clock-cells = <1>;
compatible = "st,stih416-quadfs216", "st,quadfs";
reg = <0xfe8308c4 0x44>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-pcm-0",
"clk-s-pcm-1",
"clk-s-pcm-2",
"clk-s-pcm-3";
};
CLK_S_ETH1_PHY: clockgenA0@7 {
clockgen_c: clockgen-c@fe8307d0 {
#clock-cells = <1>;
compatible = "st,stih416-quadfs432", "st,quadfs";
reg = <0xfe8307d0 0x44>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c-fs0-ch0",
"clk-s-c-vcc-sd",
"clk-s-c-fs0-ch2";
};
clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 {
#clock-cells = <0>;
compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux";
reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */
clocks = <&clk_sysin>,
<&clockgen_c 0>;
};
/*
* Add a dummy clock for the HDMI PHY for the VCC input mux
*/
clk_s_tmds_fromphy: clk-s-tmds-fromphy {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "CLK_S_ETH1_PHY";
clock-frequency = <0>;
};
clockgen_c_vcc: clockgen-c-vcc@fe8308ac {
#clock-cells = <1>;
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */
clocks = <&clk_s_vcc_hd>,
<&clockgen_c 1>,
<&clk_s_tmds_fromphy>,
<&clockgen_c 2>;
clock-output-names = "clk-s-pix-hdmi",
"clk-s-pix-dvo",
"clk-s-out-dvo",
"clk-s-pix-hd",
"clk-s-hddac",
"clk-s-denc",
"clk-s-sddac",
"clk-s-pix-main",
"clk-s-pix-aux",
"clk-s-stfe-frc-0",
"clk-s-ref-mcru",
"clk-s-slave-mcru",
"clk-s-tmds-hdmi",
"clk-s-hdmi-reject-pll",
"clk-s-thsens";
};
clockgen_d: clockgen-d@fee107e0 {
#clock-cells = <1>;
compatible = "st,stih416-quadfs216", "st,quadfs";
reg = <0xfee107e0 0x44>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-ccsc",
"clk-s-stfe-frc-1",
"clk-s-tsout-1",
"clk-s-mchi";
};
/*
* Frequency synthesizers on the MPE42
*/
clockgen_e: clockgen-e@fd3208bc {
#clock-cells = <1>;
compatible = "st,stih416-quadfs660-E", "st,quadfs";
reg = <0xfd3208bc 0xb0>;
clocks = <&clk_sysin>;
clock-output-names = "clk-m-pix-mdtp-0",
"clk-m-pix-mdtp-1",
"clk-m-pix-mdtp-2",
"clk-m-mpelpc";
};
clockgen_f: clockgen-f@fd320878 {
#clock-cells = <1>;
compatible = "st,stih416-quadfs660-F", "st,quadfs";
reg = <0xfd320878 0xf0>;
clocks = <&clk_sysin>;
clock-output-names = "clk-m-main-vidfs",
"clk-m-hva-fs",
"clk-m-fvdp-vcpu",
"clk-m-fvdp-proc-fs";
};
clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 {
#clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux";
reg = <0xfd320910 0x4>; /* SYSCFG8580 */
clocks = <&clk_m_a1_div2 0>,
<&clockgen_f 3>;
};
clk_m_hva: clk-m-hva@fd690868 {
#clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
reg = <0xfd690868 0x4>; /* SYSCFG9538 */
clocks = <&clockgen_f 1>,
<&clk_m_a1_div0 3>;
};
clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c {
#clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux";
reg = <0xfd32086c 0x4>; /* SYSCFG8539 */
clocks = <&clockgen_c_vcc 7>,
<&clockgen_f 0>;
};
clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c {
#clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux";
reg = <0xfd32086c 0x4>; /* SYSCFG8539 */
clocks = <&clockgen_c_vcc 8>,
<&clockgen_f 1>;
};
/*
* Add a dummy clock for the HDMIRx external signal clock
*/
clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clockgen_f_vcc: clockgen-f-vcc@fd32086c {
#clock-cells = <1>;
compatible = "st,stih416-clkgenf", "st,clkgen-vcc";
reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */
clocks = <&clk_m_f_vcc_hd>,
<&clk_m_f_vcc_sd>,
<&clockgen_f 0>,
<&clk_m_pix_hdmirx_sas>;
clock-output-names = "clk-m-pix-main-pipe",
"clk-m-pix-aux-pipe",
"clk-m-pix-main-cru",
"clk-m-pix-aux-cru",
"clk-m-xfer-be-compo",
"clk-m-xfer-pip-compo",
"clk-m-xfer-aux-compo",
"clk-m-vsens",
"clk-m-pix-hdmirx-0",
"clk-m-pix-hdmirx-1";
};
/*
* DDR PLL
*/
clockgen-ddr@0xfdde07d8 {
reg = <0xfdde07d8 0x110>;
clockgen_ddr_pll: clockgen-ddr-pll {
#clock-cells = <1>;
compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clockgen-ddr0",
"clockgen-ddr1";
};
};
/*
* GPU PLL
*/
clockgen-gpu@fd68ff00 {
reg = <0xfd68ff00 0x910>;
clockgen_gpu_pll: clockgen-gpu-pll {
#clock-cells = <1>;
compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32";
clocks = <&clk_sysin>;
clock-output-names = "clockgen-gpu-pll";
};
};
};
};

16
arch/arm/boot/dts/stih416-pinctrl.dtsi
View File

@ -122,6 +122,22 @@
};
};
keyscan {
pinctrl_keyscan: keyscan {
st,pins {
keyin0 = <&PIO0 2 ALT2 IN>;
keyin1 = <&PIO0 3 ALT2 IN>;
keyin2 = <&PIO0 4 ALT2 IN>;
keyin3 = <&PIO2 6 ALT2 IN>;
keyout0 = <&PIO1 6 ALT2 OUT>;
keyout1 = <&PIO1 7 ALT2 OUT>;
keyout2 = <&PIO0 6 ALT2 OUT>;
keyout3 = <&PIO2 7 ALT2 OUT>;
};
};
};
sbc_i2c0 {
pinctrl_sbc_i2c0_default: sbc_i2c0-default {
st,pins {

30
arch/arm/boot/dts/stih416.dtsi
View File

@ -89,7 +89,7 @@
status = "disabled";
reg = <0xfed32000 0x2c>;
interrupts = <0 197 0>;
clocks = <&CLK_S_ICN_REG_0>;
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>;
};
@ -102,14 +102,14 @@
interrupts = <0 210 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
clocks = <&CLK_SYSIN>;
clocks = <&clk_sysin>;
};
i2c@fed40000 {
compatible = "st,comms-ssc4-i2c";
reg = <0xfed40000 0x110>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CLK_S_ICN_REG_0>;
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@ -122,7 +122,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfed41000 0x110>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CLK_S_ICN_REG_0>;
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@ -135,7 +135,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfe540000 0x110>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CLK_SYSIN>;
clocks = <&clk_sysin>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@ -148,7 +148,7 @@
compatible = "st,comms-ssc4-i2c";
reg = <0xfe541000 0x110>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CLK_SYSIN>;
clocks = <&clk_sysin>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
@ -176,7 +176,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii0>;
clock-names = "stmmaceth";
clocks = <&CLK_S_GMAC0_PHY>;
clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>;
};
ethernet1: dwmac@fef08000 {
@ -198,7 +198,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii1>;
clock-names = "stmmaceth";
clocks = <&CLK_S_ETH1_PHY>;
clocks = <&clk_s_a0_ls CLK_ETH1_PHY>;
};
rc: rc@fe518000 {
@ -206,7 +206,7 @@
reg = <0xfe518000 0x234>;
interrupts = <0 203 0>;
rx-mode = "infrared";
clocks = <&CLK_SYSIN>;
clocks = <&clk_sysin>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ir>;
resets = <&softreset STIH416_IRB_SOFTRESET>;
@ -224,5 +224,17 @@
status = "disabled";
};
keyscan: keyscan@fe4b0000 {
compatible = "st,sti-keyscan";
status = "disabled";
reg = <0xfe4b0000 0x2000>;
interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
clocks = <&clk_sysin>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_keyscan>;
resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
<&softreset STIH416_KEYSCAN_SOFTRESET>;
};
};
};

25
arch/arm/boot/dts/stih41x-b2000.dtsi
View File

@ -6,6 +6,7 @@
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <dt-bindings/input/input.h>
/ {
memory{
@ -14,7 +15,7 @@
};
chosen {
bootargs = "console=ttyAS0,115200";
bootargs = "console=ttyAS0,115200 clk_ignore_unused";
linux,stdout-path = &serial2;
};
@ -68,5 +69,27 @@
snps,reset-active-low;
snps,reset-delays-us = <0 10000 10000>;
};
keyscan: keyscan@fe4b0000 {
keypad,num-rows = <4>;
keypad,num-columns = <4>;
st,debounce-us = <5000>;
linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13)
MATRIX_KEY(0x00, 0x01, KEY_F9)
MATRIX_KEY(0x00, 0x02, KEY_F5)
MATRIX_KEY(0x00, 0x03, KEY_F1)
MATRIX_KEY(0x01, 0x00, KEY_F14)
MATRIX_KEY(0x01, 0x01, KEY_F10)
MATRIX_KEY(0x01, 0x02, KEY_F6)
MATRIX_KEY(0x01, 0x03, KEY_F2)
MATRIX_KEY(0x02, 0x00, KEY_F15)
MATRIX_KEY(0x02, 0x01, KEY_F11)
MATRIX_KEY(0x02, 0x02, KEY_F7)
MATRIX_KEY(0x02, 0x03, KEY_F3)
MATRIX_KEY(0x03, 0x00, KEY_F16)
MATRIX_KEY(0x03, 0x01, KEY_F12)
MATRIX_KEY(0x03, 0x02, KEY_F8)
MATRIX_KEY(0x03, 0x03, KEY_F4) >;
};
};
};

2
arch/arm/boot/dts/stih41x-b2020.dtsi
View File

@ -14,7 +14,7 @@
};
chosen {
bootargs = "console=ttyAS0,115200";
bootargs = "console=ttyAS0,115200 clk_ignore_unused";
linux,stdout-path = &sbc_serial1;
};

7
arch/arm/boot/dts/stih41x.dtsi
View File

@ -1,3 +1,10 @@
/*
* Copyright (C) 2014 STMicroelectronics Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/ {
#address-cells = <1>;
#size-cells = <1>;

1
drivers/reset/sti/reset-stih415.c
View File

@ -73,6 +73,7 @@ static const struct syscfg_reset_channel_data stih415_softresets[] = {
[STIH415_USB0_SOFTRESET] = STIH415_SRST_REAR(SYSCFG_376, 9),
[STIH415_USB1_SOFTRESET] = STIH415_SRST_REAR(SYSCFG_376, 10),
[STIH415_USB2_SOFTRESET] = STIH415_SRST_REAR(SYSCFG_376, 11),
[STIH415_KEYSCAN_SOFTRESET] = STIH415_SRST_LPM(LPM_SYSCFG_1, 8),
};
static struct syscfg_reset_controller_data stih415_powerdown_controller = {

1
drivers/reset/sti/reset-stih416.c
View File

@ -104,6 +104,7 @@ static const struct syscfg_reset_channel_data stih416_softresets[] = {
[STIH416_COMPO_A_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 4),
[STIH416_VP8_DEC_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 10),
[STIH416_VTG_MAIN_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 16),
[STIH416_KEYSCAN_SOFTRESET] = STIH416_SRST_LPM(LPM_SYSCFG_1, 8),
};
static struct syscfg_reset_controller_data stih416_powerdown_controller = {

15
include/dt-bindings/clock/stih415-clks.h Normal file
View File

@ -0,0 +1,15 @@
/*
* This header provides constants clk index STMicroelectronics
* STiH415 SoC.
*/
#ifndef _CLK_STIH415
#define _CLK_STIH415
/* CLOCKGEN A0 */
#define CLK_ICN_REG 0
#define CLK_ETH1_PHY 4
/* CLOCKGEN A1 */
#define CLK_GMAC0_PHY 3
#endif

15
include/dt-bindings/clock/stih416-clks.h Normal file
View File

@ -0,0 +1,15 @@
/*
* This header provides constants clk index STMicroelectronics
* STiH416 SoC.
*/
#ifndef _CLK_STIH416
#define _CLK_STIH416
/* CLOCKGEN A0 */
#define CLK_ICN_REG 0
#define CLK_ETH1_PHY 4
/* CLOCKGEN A1 */
#define CLK_GMAC0_PHY 3
#endif

1
include/dt-bindings/reset-controller/stih415-resets.h
View File

@ -22,5 +22,6 @@
#define STIH415_USB0_SOFTRESET 3
#define STIH415_USB1_SOFTRESET 4
#define STIH415_USB2_SOFTRESET 5
#define STIH415_KEYSCAN_SOFTRESET 6
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */

1
include/dt-bindings/reset-controller/stih416-resets.h
View File

@ -46,5 +46,6 @@
#define STIH416_COMPO_A_SOFTRESET 25
#define STIH416_VP8_DEC_SOFTRESET 26
#define STIH416_VTG_MAIN_SOFTRESET 27
#define STIH416_KEYSCAN_SOFTRESET 28
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */