mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-28 23:23:55 +08:00
ARM: OMAP2: Remove old 24xx specific clock functions
Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Paul Walmsley
Tony Lindgren
parent
e32744b02d
commit
2150ef46f8
@ -109,29 +109,6 @@ static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
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return dpll_clk;
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}
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static void omap2_followparent_recalc(struct clk *clk)
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{
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followparent_recalc(clk);
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}
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static void omap2_propagate_rate(struct clk * clk)
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{
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if (!(clk->flags & RATE_FIXED))
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clk->rate = clk->parent->rate;
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propagate_rate(clk);
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}
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#ifdef OLD_CK
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static void omap2_set_osc_ck(int enable)
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{
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if (enable)
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PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
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else
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PRCM_CLKSRC_CTRL |= 0x3 << 3;
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}
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#endif /* OLD_CK */
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/* Enable an APLL if off */
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static int omap2_clk_fixed_enable(struct clk *clk)
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{
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@ -163,84 +140,6 @@ static int omap2_clk_fixed_enable(struct clk *clk)
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return 0;
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}
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#ifdef OLD_CK
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static void omap2_clk_wait_ready(struct clk *clk)
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{
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unsigned long reg, other_reg, st_reg;
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u32 bit;
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int i;
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reg = (unsigned long) clk->enable_reg;
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if (reg == (unsigned long) &CM_FCLKEN1_CORE ||
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reg == (unsigned long) &CM_FCLKEN2_CORE)
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other_reg = (reg & ~0xf0) | 0x10;
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else if (reg == (unsigned long) &CM_ICLKEN1_CORE ||
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reg == (unsigned long) &CM_ICLKEN2_CORE)
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other_reg = (reg & ~0xf0) | 0x00;
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else
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return;
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/* No check for DSS or cam clocks */
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if ((reg & 0x0f) == 0) {
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if (clk->enable_bit <= 1 || clk->enable_bit == 31)
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return;
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}
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/* Check if both functional and interface clocks
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* are running. */
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bit = 1 << clk->enable_bit;
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if (!(__raw_readl(other_reg) & bit))
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return;
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st_reg = (other_reg & ~0xf0) | 0x20;
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i = 0;
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while (!(__raw_readl(st_reg) & bit)) {
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i++;
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if (i == 100000) {
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printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
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break;
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}
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}
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if (i)
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pr_debug("Clock %s stable after %d loops\n", clk->name, i);
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}
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/* Enables clock without considering parent dependencies or use count
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* REVISIT: Maybe change this to use clk->enable like on omap1?
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*/
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static int _omap2_clk_enable(struct clk * clk)
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{
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u32 regval32;
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if (clk->flags & ALWAYS_ENABLED)
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return 0;
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if (unlikely(clk == &osc_ck)) {
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omap2_set_osc_ck(1);
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return 0;
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}
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if (unlikely(clk->enable_reg == 0)) {
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printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
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clk->name);
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return 0;
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}
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if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
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omap2_clk_fixed_enable(clk);
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return 0;
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}
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regval32 = __raw_readl(clk->enable_reg);
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regval32 |= (1 << clk->enable_bit);
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__raw_writel(regval32, clk->enable_reg);
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wmb();
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omap2_clk_wait_ready(clk);
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return 0;
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}
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#endif /* OLD_CK */
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/* Stop APLL */
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static void omap2_clk_fixed_disable(struct clk *clk)
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{
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@ -251,65 +150,6 @@ static void omap2_clk_fixed_disable(struct clk *clk)
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cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
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}
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#ifdef OLD_CK
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/* Disables clock without considering parent dependencies or use count */
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static void _omap2_clk_disable(struct clk *clk)
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{
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u32 regval32;
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if (unlikely(clk == &osc_ck)) {
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omap2_set_osc_ck(0);
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return;
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}
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if (clk->enable_reg == 0)
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return;
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if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
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omap2_clk_fixed_disable(clk);
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return;
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}
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regval32 = __raw_readl(clk->enable_reg);
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regval32 &= ~(1 << clk->enable_bit);
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__raw_writel(regval32, clk->enable_reg);
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wmb();
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}
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static int omap2_clk_enable(struct clk *clk)
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{
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int ret = 0;
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if (clk->usecount++ == 0) {
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if (likely((u32)clk->parent))
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ret = omap2_clk_enable(clk->parent);
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if (unlikely(ret != 0)) {
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clk->usecount--;
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return ret;
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}
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ret = _omap2_clk_enable(clk);
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if (unlikely(ret != 0) && clk->parent) {
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omap2_clk_disable(clk->parent);
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clk->usecount--;
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}
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}
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return ret;
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}
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static void omap2_clk_disable(struct clk *clk)
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{
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if (clk->usecount > 0 && !(--clk->usecount)) {
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_omap2_clk_disable(clk);
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if (likely((u32)clk->parent))
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omap2_clk_disable(clk->parent);
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}
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}
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#endif /* OLD_CK */
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/*
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* Uses the current prcm set to tell if a rate is valid.
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* You can go slower, but not faster within a given rate set.
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@ -343,195 +183,6 @@ static u32 omap2_dpll_round_rate(unsigned long target_rate)
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}
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#ifdef OLD_CK
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/*
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* Used for clocks that are part of CLKSEL_xyz governed clocks.
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* REVISIT: Maybe change to use clk->enable() functions like on omap1?
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*/
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static void omap2_clksel_recalc(struct clk * clk)
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{
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u32 fixed = 0, div = 0;
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if (clk == &dpll_ck) {
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clk->rate = omap2_get_dpll_rate(clk);
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fixed = 1;
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div = 0;
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}
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if (clk == &iva1_mpu_int_ifck) {
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div = 2;
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fixed = 1;
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}
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if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
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clk->rate = sys_ck.rate;
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return;
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}
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if (!fixed) {
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div = omap2_clksel_get_divisor(clk);
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if (div == 0)
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return;
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}
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if (div != 0) {
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if (unlikely(clk->rate == clk->parent->rate / div))
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return;
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clk->rate = clk->parent->rate / div;
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}
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if (unlikely(clk->flags & RATE_PROPAGATES))
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propagate_rate(clk);
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}
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/*
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* Finds best divider value in an array based on the source and target
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* rates. The divider array must be sorted with smallest divider first.
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*/
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static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
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u32 src_rate, u32 tgt_rate)
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{
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int i, test_rate;
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if (div_array == NULL)
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return ~1;
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for (i=0; i < size; i++) {
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test_rate = src_rate / *div_array;
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if (test_rate <= tgt_rate)
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return *div_array;
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++div_array;
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}
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return ~0; /* No acceptable divider */
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}
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/*
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* Find divisor for the given clock and target rate.
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*
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* Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
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* they are only settable as part of virtual_prcm set.
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*/
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static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
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u32 *new_div)
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{
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u32 gfx_div[] = {2, 3, 4};
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u32 sysclkout_div[] = {1, 2, 4, 8, 16};
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u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
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u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
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u32 best_div = ~0, asize = 0;
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u32 *div_array = NULL;
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switch (tclk->flags & SRC_RATE_SEL_MASK) {
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case CM_GFX_SEL1:
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asize = 3;
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div_array = gfx_div;
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break;
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case CM_PLL_SEL1:
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return omap2_dpll_round_rate(target_rate);
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case CM_SYSCLKOUT_SEL1:
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asize = 5;
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div_array = sysclkout_div;
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break;
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case CM_CORE_SEL1:
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if(tclk == &dss1_fck){
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if(tclk->parent == &core_ck){
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asize = 10;
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div_array = dss1_div;
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} else {
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*new_div = 0; /* fixed clk */
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return(tclk->parent->rate);
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}
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} else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
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if(tclk->parent == &core_ck){
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asize = 10;
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div_array = vylnq_div;
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} else {
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*new_div = 0; /* fixed clk */
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return(tclk->parent->rate);
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}
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}
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break;
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}
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best_div = omap2_divider_from_table(asize, div_array,
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tclk->parent->rate, target_rate);
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if (best_div == ~0){
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*new_div = 1;
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return best_div; /* signal error */
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}
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*new_div = best_div;
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return (tclk->parent->rate / best_div);
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}
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/* Given a clock and a rate apply a clock specific rounding function */
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static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
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{
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u32 new_div = 0;
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int valid_rate;
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if (clk->flags & RATE_FIXED)
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return clk->rate;
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if (clk->flags & RATE_CKCTL) {
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valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
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return valid_rate;
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}
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if (clk->round_rate != 0)
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return clk->round_rate(clk, rate);
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return clk->rate;
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}
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/*
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* Check the DLL lock state, and return tue if running in unlock mode.
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* This is needed to compensate for the shifted DLL value in unlock mode.
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*/
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static u32 omap2_dll_force_needed(void)
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{
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u32 dll_state = SDRC_DLLA_CTRL; /* dlla and dllb are a set */
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if ((dll_state & (1 << 2)) == (1 << 2))
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return 1;
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else
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return 0;
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}
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static u32 omap2_reprogram_sdrc(u32 level, u32 force)
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{
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u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
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u32 prev = curr_perf_level, flags;
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if ((curr_perf_level == level) && !force)
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return prev;
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m_type = omap2_memory_get_type();
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slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
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fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
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if (level == PRCM_HALF_SPEED) {
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local_irq_save(flags);
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PRCM_VOLTSETUP = 0xffff;
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omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
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slow_dll_ctrl, m_type);
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curr_perf_level = PRCM_HALF_SPEED;
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local_irq_restore(flags);
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}
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if (level == PRCM_FULL_SPEED) {
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local_irq_save(flags);
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PRCM_VOLTSETUP = 0xffff;
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omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
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fast_dll_ctrl, m_type);
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curr_perf_level = PRCM_FULL_SPEED;
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local_irq_restore(flags);
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}
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return prev;
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}
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#endif /* OLD_CK */
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static void omap2_dpll_recalc(struct clk *clk)
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{
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clk->rate = omap2_get_dpll_rate_24xx(clk);
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@ -656,359 +307,6 @@ static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
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return highest_rate;
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}
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#ifdef OLD_CK
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/*
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* omap2_convert_field_to_div() - turn field value into integer divider
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*/
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static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
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{
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u32 i;
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u32 clkout_array[] = {1, 2, 4, 8, 16};
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if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
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for (i = 0; i < 5; i++) {
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if (field_val == i)
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return clkout_array[i];
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}
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return ~0;
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} else
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return field_val;
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}
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/*
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* Returns the CLKSEL divider register value
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* REVISIT: This should be cleaned up to work nicely with void __iomem *
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*/
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static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
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struct clk *clk)
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{
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int ret = ~0;
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u32 reg_val, div_off;
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u32 div_addr = 0;
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u32 mask = ~0;
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div_off = clk->rate_offset;
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switch ((*div_sel & SRC_RATE_SEL_MASK)) {
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case CM_MPU_SEL1:
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div_addr = (u32)&CM_CLKSEL_MPU;
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mask = 0x1f;
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break;
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case CM_DSP_SEL1:
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div_addr = (u32)&CM_CLKSEL_DSP;
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if (cpu_is_omap2420()) {
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if ((div_off == 0) || (div_off == 8))
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mask = 0x1f;
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else if (div_off == 5)
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mask = 0x3;
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} else if (cpu_is_omap2430()) {
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if (div_off == 0)
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mask = 0x1f;
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else if (div_off == 5)
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mask = 0x3;
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}
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break;
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case CM_GFX_SEL1:
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div_addr = (u32)&CM_CLKSEL_GFX;
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if (div_off == 0)
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mask = 0x7;
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break;
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case CM_MODEM_SEL1:
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div_addr = (u32)&CM_CLKSEL_MDM;
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if (div_off == 0)
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mask = 0xf;
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break;
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case CM_SYSCLKOUT_SEL1:
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div_addr = (u32)&PRCM_CLKOUT_CTRL;
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if ((div_off == 3) || (div_off == 11))
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mask= 0x3;
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break;
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case CM_CORE_SEL1:
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div_addr = (u32)&CM_CLKSEL1_CORE;
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switch (div_off) {
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case 0: /* l3 */
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case 8: /* dss1 */
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case 15: /* vylnc-2420 */
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case 20: /* ssi */
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mask = 0x1f; break;
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case 5: /* l4 */
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mask = 0x3; break;
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case 13: /* dss2 */
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mask = 0x1; break;
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case 25: /* usb */
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mask = 0x7; break;
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}
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}
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*field_mask = mask;
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if (unlikely(mask == ~0))
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div_addr = 0;
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*div_sel = div_addr;
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if (unlikely(div_addr == 0))
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return ret;
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/* Isolate field */
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reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
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/* Normalize back to divider value */
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reg_val >>= div_off;
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return reg_val;
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}
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/*
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* Return divider to be applied to parent clock.
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* Return 0 on error.
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*/
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static u32 omap2_clksel_get_divisor(struct clk *clk)
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{
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int ret = 0;
|
||||
u32 div, div_sel, div_off, field_mask, field_val;
|
||||
|
||||
/* isolate control register */
|
||||
div_sel = (SRC_RATE_SEL_MASK & clk->flags);
|
||||
|
||||
div_off = clk->rate_offset;
|
||||
field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
|
||||
if (div_sel == 0)
|
||||
return ret;
|
||||
|
||||
div_sel = (SRC_RATE_SEL_MASK & clk->flags);
|
||||
div = omap2_clksel_to_divisor(div_sel, field_val);
|
||||
|
||||
return div;
|
||||
}
|
||||
|
||||
/* Set the clock rate for a clock source */
|
||||
static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
void __iomem * reg;
|
||||
u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
|
||||
u32 new_div = 0;
|
||||
|
||||
if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
|
||||
if (clk == &dpll_ck)
|
||||
return omap2_reprogram_dpll(clk, rate);
|
||||
|
||||
/* Isolate control register */
|
||||
div_sel = (SRC_RATE_SEL_MASK & clk->flags);
|
||||
div_off = clk->rate_offset;
|
||||
|
||||
validrate = omap2_clksel_round_rate(clk, rate, &new_div);
|
||||
if (validrate != rate)
|
||||
return(ret);
|
||||
|
||||
field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
|
||||
if (div_sel == 0)
|
||||
return ret;
|
||||
|
||||
if (clk->flags & CM_SYSCLKOUT_SEL1) {
|
||||
switch (new_div) {
|
||||
case 16:
|
||||
field_val = 4;
|
||||
break;
|
||||
case 8:
|
||||
field_val = 3;
|
||||
break;
|
||||
case 4:
|
||||
field_val = 2;
|
||||
break;
|
||||
case 2:
|
||||
field_val = 1;
|
||||
break;
|
||||
case 1:
|
||||
field_val = 0;
|
||||
break;
|
||||
}
|
||||
} else
|
||||
field_val = new_div;
|
||||
|
||||
reg = (void __iomem *)div_sel;
|
||||
|
||||
reg_val = __raw_readl(reg);
|
||||
reg_val &= ~(field_mask << div_off);
|
||||
reg_val |= (field_val << div_off);
|
||||
__raw_writel(reg_val, reg);
|
||||
wmb();
|
||||
clk->rate = clk->parent->rate / field_val;
|
||||
|
||||
if (clk->flags & DELAYED_APP) {
|
||||
__raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
|
||||
wmb();
|
||||
}
|
||||
ret = 0;
|
||||
} else if (clk->set_rate != 0)
|
||||
ret = clk->set_rate(clk, rate);
|
||||
|
||||
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
|
||||
propagate_rate(clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Converts encoded control register address into a full address */
|
||||
static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
|
||||
struct clk *src_clk, u32 *field_mask)
|
||||
{
|
||||
u32 val = ~0, src_reg_addr = 0, mask = 0;
|
||||
|
||||
/* Find target control register.*/
|
||||
switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
|
||||
case CM_CORE_SEL1:
|
||||
src_reg_addr = (u32)&CM_CLKSEL1_CORE;
|
||||
if (reg_offset == 13) { /* DSS2_fclk */
|
||||
mask = 0x1;
|
||||
if (src_clk == &sys_ck)
|
||||
val = 0;
|
||||
if (src_clk == &func_48m_ck)
|
||||
val = 1;
|
||||
} else if (reg_offset == 8) { /* DSS1_fclk */
|
||||
mask = 0x1f;
|
||||
if (src_clk == &sys_ck)
|
||||
val = 0;
|
||||
else if (src_clk == &core_ck) /* divided clock */
|
||||
val = 0x10; /* rate needs fixing */
|
||||
} else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
|
||||
mask = 0x1F;
|
||||
if(src_clk == &func_96m_ck)
|
||||
val = 0;
|
||||
else if (src_clk == &core_ck)
|
||||
val = 0x10;
|
||||
}
|
||||
break;
|
||||
case CM_CORE_SEL2:
|
||||
src_reg_addr = (u32)&CM_CLKSEL2_CORE;
|
||||
mask = 0x3;
|
||||
if (src_clk == &func_32k_ck)
|
||||
val = 0x0;
|
||||
if (src_clk == &sys_ck)
|
||||
val = 0x1;
|
||||
if (src_clk == &alt_ck)
|
||||
val = 0x2;
|
||||
break;
|
||||
case CM_WKUP_SEL1:
|
||||
src_reg_addr = (u32)&CM_CLKSEL_WKUP;
|
||||
mask = 0x3;
|
||||
if (src_clk == &func_32k_ck)
|
||||
val = 0x0;
|
||||
if (src_clk == &sys_ck)
|
||||
val = 0x1;
|
||||
if (src_clk == &alt_ck)
|
||||
val = 0x2;
|
||||
break;
|
||||
case CM_PLL_SEL1:
|
||||
src_reg_addr = (u32)&CM_CLKSEL1_PLL;
|
||||
mask = 0x1;
|
||||
if (reg_offset == 0x3) {
|
||||
if (src_clk == &apll96_ck)
|
||||
val = 0;
|
||||
if (src_clk == &alt_ck)
|
||||
val = 1;
|
||||
}
|
||||
else if (reg_offset == 0x5) {
|
||||
if (src_clk == &apll54_ck)
|
||||
val = 0;
|
||||
if (src_clk == &alt_ck)
|
||||
val = 1;
|
||||
}
|
||||
break;
|
||||
case CM_PLL_SEL2:
|
||||
src_reg_addr = (u32)&CM_CLKSEL2_PLL;
|
||||
mask = 0x3;
|
||||
if (src_clk == &func_32k_ck)
|
||||
val = 0x0;
|
||||
if (src_clk == &dpll_ck)
|
||||
val = 0x2;
|
||||
break;
|
||||
case CM_SYSCLKOUT_SEL1:
|
||||
src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
|
||||
mask = 0x3;
|
||||
if (src_clk == &dpll_ck)
|
||||
val = 0;
|
||||
if (src_clk == &sys_ck)
|
||||
val = 1;
|
||||
if (src_clk == &func_96m_ck)
|
||||
val = 2;
|
||||
if (src_clk == &func_54m_ck)
|
||||
val = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
if (val == ~0) /* Catch errors in offset */
|
||||
*type_to_addr = 0;
|
||||
else
|
||||
*type_to_addr = src_reg_addr;
|
||||
*field_mask = mask;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
|
||||
{
|
||||
void __iomem * reg;
|
||||
u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (unlikely(clk->flags & CONFIG_PARTICIPANT))
|
||||
return ret;
|
||||
|
||||
if (clk->flags & SRC_SEL_MASK) { /* On-chip SEL collection */
|
||||
src_sel = (SRC_RATE_SEL_MASK & clk->flags);
|
||||
src_off = clk->src_offset;
|
||||
|
||||
if (src_sel == 0)
|
||||
goto set_parent_error;
|
||||
|
||||
field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
|
||||
&field_mask);
|
||||
|
||||
reg = (void __iomem *)src_sel;
|
||||
|
||||
if (clk->usecount > 0)
|
||||
_omap2_clk_disable(clk);
|
||||
|
||||
/* Set new source value (previous dividers if any in effect) */
|
||||
reg_val = __raw_readl(reg) & ~(field_mask << src_off);
|
||||
reg_val |= (field_val << src_off);
|
||||
__raw_writel(reg_val, reg);
|
||||
wmb();
|
||||
|
||||
if (clk->flags & DELAYED_APP) {
|
||||
__raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
|
||||
wmb();
|
||||
}
|
||||
if (clk->usecount > 0)
|
||||
_omap2_clk_enable(clk);
|
||||
|
||||
clk->parent = new_parent;
|
||||
|
||||
/* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
|
||||
if ((new_parent == &core_ck) && (clk == &dss1_fck))
|
||||
clk->rate = new_parent->rate / 0x10;
|
||||
else
|
||||
clk->rate = new_parent->rate;
|
||||
|
||||
if (unlikely(clk->flags & RATE_PROPAGATES))
|
||||
propagate_rate(clk);
|
||||
|
||||
return 0;
|
||||
} else {
|
||||
clk->parent = new_parent;
|
||||
rate = new_parent->rate;
|
||||
omap2_clk_set_rate(clk, rate);
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
set_parent_error:
|
||||
return ret;
|
||||
}
|
||||
#endif /* OLD_CK */
|
||||
|
||||
/* Sets basic clocks based on the specified rate */
|
||||
static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
@ -1090,26 +388,6 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Omap2 clock reset and init functions
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef CONFIG_OMAP_RESET_CLOCKS
|
||||
static void __init omap2_clk_disable_unused(struct clk *clk)
|
||||
{
|
||||
u32 regval32;
|
||||
|
||||
regval32 = __raw_readl(clk->enable_reg);
|
||||
if ((regval32 & (1 << clk->enable_bit)) == 0)
|
||||
return;
|
||||
|
||||
printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
|
||||
_omap2_clk_disable(clk);
|
||||
}
|
||||
#else
|
||||
#define omap2_clk_disable_unused NULL
|
||||
#endif
|
||||
|
||||
static struct clk_functions omap2_clk_functions = {
|
||||
.clk_enable = omap2_clk_enable,
|
||||
.clk_disable = omap2_clk_disable,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user