renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-23 12:43:55 +08:00
Code

x86/PCI: Clarify AMD Fam10h config access restrictions comment

Browse Source 
Clarify the comment about AMD Fam10h config access restrictions, fix typos,
and add a reference to the specification.

[bhelgaas: streamline]
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
This commit is contained in:
Tomasz Nowicki 2015-05-26 20:49:15 +08:00 committed by Bjorn Helgaas
parent 4066df6345
commit 21461775f3
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/x86/include/asm/pci_x86.h
View File

@ -151,11 +151,11 @@ extern struct list_head pci_mmcfg_list;
#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
/*
* AMD Fam10h CPUs are buggy, and cannot access MMIO config space
* on their northbrige except through the * %eax register. As such, you MUST
* NOT use normal IOMEM accesses, you need to only use the magic mmio-config
* accessor functions.
* In fact just use pci_config_*, nothing else please.
* On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use
* %eax. No other source or target registers may be used. The following
* mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's
* Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1,
* "MMIO Configuration Coding Requirements".
*/
static inline unsigned char mmio_config_readb(void __iomem *pos)
{