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A number of fixes for this release, but mostly:
- A fixup for the A10 CSI DT binding merged during the 5.4-rc1 window - A fix for a dt-binding error - Addition of phy regulator delays - The PMU on the A64 was found to be non-functional, so we've dropped it for now -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXa/4RQAKCRDj7w1vZxhR xU3XAQDYuCixpCCftKIhjcz+oultXqAJysDEE44dATwT1YfINgD/eBSwBw1l/Ni7 yOumUvRZ1fJC3NO8e7vh9cYN9yy5tgw= =3/ru -----END PGP SIGNATURE----- Merge tag 'sunxi-fixes-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes A number of fixes for this release, but mostly: - A fixup for the A10 CSI DT binding merged during the 5.4-rc1 window - A fix for a dt-binding error - Addition of phy regulator delays - The PMU on the A64 was found to be non-functional, so we've dropped it for now * tag 'sunxi-fixes-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: dts: sun7i: Drop the module clock from the device tree dt-bindings: media: sun4i-csi: Drop the module clock media: dt-bindings: Fix building error for dt_binding_check arm64: dts: allwinner: a64: sopine-baseboard: Add PHY regulator delay arm64: dts: allwinner: a64: Drop PMU node arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator delay Link: https://lore.kernel.org/r/80085a57-c40f-4bed-a9c3-19858d87564e.lettre@localhost Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
21397ae00f
@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/allwinner,sun4i-a10-csi.yaml#
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$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings
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@ -27,14 +27,12 @@ properties:
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clocks:
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items:
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- description: The CSI interface clock
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- description: The CSI module clock
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- description: The CSI ISP clock
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- description: The CSI DRAM clock
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clock-names:
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items:
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- const: bus
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- const: mod
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- const: isp
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- const: ram
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@ -89,9 +87,8 @@ examples:
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compatible = "allwinner,sun7i-a20-csi0";
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reg = <0x01c09000 0x1000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
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<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
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clock-names = "bus", "mod", "isp", "ram";
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clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
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clock-names = "bus", "isp", "ram";
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resets = <&ccu RST_CSI0>;
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port {
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@ -380,9 +380,8 @@
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compatible = "allwinner,sun7i-a20-csi0";
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reg = <0x01c09000 0x1000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
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<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
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clock-names = "bus", "mod", "isp", "ram";
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clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
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clock-names = "bus", "isp", "ram";
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resets = <&ccu RST_CSI0>;
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status = "disabled";
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};
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@ -63,3 +63,12 @@
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reg = <1>;
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};
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};
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®_dc1sw {
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/*
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* Ethernet PHY needs 30ms to properly power up and some more
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* to initialize. 100ms should be plenty of time to finish
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* whole process.
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*/
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regulator-enable-ramp-delay = <100000>;
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};
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@ -159,6 +159,12 @@
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};
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®_dc1sw {
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/*
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* Ethernet PHY needs 30ms to properly power up and some more
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* to initialize. 100ms should be plenty of time to finish
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* whole process.
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*/
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regulator-enable-ramp-delay = <100000>;
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regulator-name = "vcc-phy";
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};
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@ -142,15 +142,6 @@
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clock-output-names = "ext-osc32k";
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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