mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-19 18:53:52 +08:00
sdhci: scatter-gather (ADMA) support
Add support for the scatter-gather DMA mode present on newer controllers. As the mode requires 32-bit alignment, non-aligned chunks are handled by using a bounce buffer. Also add some new quirks to handle controllers that have bugs in the ADMA engine. Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
This commit is contained in:
Pierre Ossman
parent
93fc48c785
commit
2134a922c6
@ -142,6 +142,7 @@ static int jmicron_probe(struct sdhci_pci_chip *chip)
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if (chip->pdev->revision == 0) {
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chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
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SDHCI_QUIRK_32BIT_DMA_SIZE |
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SDHCI_QUIRK_32BIT_ADMA_SIZE |
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SDHCI_QUIRK_RESET_AFTER_REQUEST;
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}
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@ -206,6 +207,22 @@ static void jmicron_enable_mmc(struct sdhci_host *host, int on)
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static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
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{
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if (slot->chip->pdev->revision == 0) {
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u16 version;
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version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
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version = (version & SDHCI_VENDOR_VER_MASK) >>
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SDHCI_VENDOR_VER_SHIFT;
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/*
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* Older versions of the chip have lots of nasty glitches
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* in the ADMA engine. It's best just to avoid it
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* completely.
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*/
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if (version < 0xAC)
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slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
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}
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/*
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* The secondary interface requires a bit set to get the
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* interrupts.
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@ -124,7 +124,8 @@ static void sdhci_init(struct sdhci_host *host)
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SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
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SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
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SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
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SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
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SDHCI_INT_ADMA_ERROR;
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writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
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writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
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@ -314,6 +315,196 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
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DBG("PIO transfer complete.\n");
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}
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static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
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{
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local_irq_save(*flags);
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return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
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}
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static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
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{
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kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
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local_irq_restore(*flags);
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}
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static void sdhci_adma_table_pre(struct sdhci_host *host,
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struct mmc_data *data)
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{
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int direction;
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u8 *desc;
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u8 *align;
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dma_addr_t addr;
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dma_addr_t align_addr;
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int len, offset;
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struct scatterlist *sg;
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int i;
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char *buffer;
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unsigned long flags;
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/*
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* The spec does not specify endianness of descriptor table.
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* We currently guess that it is LE.
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*/
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if (data->flags & MMC_DATA_READ)
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direction = DMA_FROM_DEVICE;
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else
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direction = DMA_TO_DEVICE;
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/*
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* The ADMA descriptor table is mapped further down as we
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* need to fill it with data first.
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*/
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host->align_addr = dma_map_single(mmc_dev(host->mmc),
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host->align_buffer, 128 * 4, direction);
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BUG_ON(host->align_addr & 0x3);
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host->sg_count = dma_map_sg(mmc_dev(host->mmc),
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data->sg, data->sg_len, direction);
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desc = host->adma_desc;
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align = host->align_buffer;
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align_addr = host->align_addr;
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for_each_sg(data->sg, sg, host->sg_count, i) {
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addr = sg_dma_address(sg);
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len = sg_dma_len(sg);
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/*
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* The SDHCI specification states that ADMA
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* addresses must be 32-bit aligned. If they
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* aren't, then we use a bounce buffer for
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* the (up to three) bytes that screw up the
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* alignment.
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*/
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offset = (4 - (addr & 0x3)) & 0x3;
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if (offset) {
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if (data->flags & MMC_DATA_WRITE) {
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buffer = sdhci_kmap_atomic(sg, &flags);
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memcpy(align, buffer, offset);
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sdhci_kunmap_atomic(buffer, &flags);
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}
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desc[7] = (align_addr >> 24) & 0xff;
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desc[6] = (align_addr >> 16) & 0xff;
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desc[5] = (align_addr >> 8) & 0xff;
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desc[4] = (align_addr >> 0) & 0xff;
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BUG_ON(offset > 65536);
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desc[3] = (offset >> 8) & 0xff;
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desc[2] = (offset >> 0) & 0xff;
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desc[1] = 0x00;
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desc[0] = 0x21; /* tran, valid */
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align += 4;
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align_addr += 4;
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desc += 8;
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addr += offset;
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len -= offset;
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}
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desc[7] = (addr >> 24) & 0xff;
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desc[6] = (addr >> 16) & 0xff;
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desc[5] = (addr >> 8) & 0xff;
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desc[4] = (addr >> 0) & 0xff;
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BUG_ON(len > 65536);
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desc[3] = (len >> 8) & 0xff;
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desc[2] = (len >> 0) & 0xff;
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desc[1] = 0x00;
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desc[0] = 0x21; /* tran, valid */
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desc += 8;
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/*
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* If this triggers then we have a calculation bug
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* somewhere. :/
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*/
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WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
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}
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/*
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* Add a terminating entry.
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*/
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desc[7] = 0;
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desc[6] = 0;
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desc[5] = 0;
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desc[4] = 0;
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desc[3] = 0;
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desc[2] = 0;
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desc[1] = 0x00;
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desc[0] = 0x03; /* nop, end, valid */
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/*
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* Resync align buffer as we might have changed it.
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*/
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if (data->flags & MMC_DATA_WRITE) {
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dma_sync_single_for_device(mmc_dev(host->mmc),
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host->align_addr, 128 * 4, direction);
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}
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host->adma_addr = dma_map_single(mmc_dev(host->mmc),
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host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
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BUG_ON(host->adma_addr & 0x3);
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}
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static void sdhci_adma_table_post(struct sdhci_host *host,
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struct mmc_data *data)
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{
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int direction;
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struct scatterlist *sg;
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int i, size;
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u8 *align;
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char *buffer;
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unsigned long flags;
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if (data->flags & MMC_DATA_READ)
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direction = DMA_FROM_DEVICE;
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else
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direction = DMA_TO_DEVICE;
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dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
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(128 * 2 + 1) * 4, DMA_TO_DEVICE);
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dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
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128 * 4, direction);
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if (data->flags & MMC_DATA_READ) {
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dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
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data->sg_len, direction);
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align = host->align_buffer;
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for_each_sg(data->sg, sg, host->sg_count, i) {
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if (sg_dma_address(sg) & 0x3) {
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size = 4 - (sg_dma_address(sg) & 0x3);
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buffer = sdhci_kmap_atomic(sg, &flags);
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memcpy(buffer, align, size);
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sdhci_kunmap_atomic(buffer, &flags);
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align += 4;
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}
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}
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}
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dma_unmap_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, direction);
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}
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static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
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{
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u8 count;
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@ -363,6 +554,7 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
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static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
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{
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u8 count;
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u8 ctrl;
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WARN_ON(host->data);
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@ -383,35 +575,104 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
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if (host->flags & SDHCI_USE_DMA)
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host->flags |= SDHCI_REQ_USE_DMA;
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if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
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(host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
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((data->blksz * data->blocks) & 0x3))) {
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DBG("Reverting to PIO because of transfer size (%d)\n",
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data->blksz * data->blocks);
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host->flags &= ~SDHCI_REQ_USE_DMA;
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/*
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* FIXME: This doesn't account for merging when mapping the
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* scatterlist.
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*/
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if (host->flags & SDHCI_REQ_USE_DMA) {
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int broken, i;
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struct scatterlist *sg;
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broken = 0;
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if (host->flags & SDHCI_USE_ADMA) {
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if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
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broken = 1;
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} else {
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if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
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broken = 1;
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}
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if (unlikely(broken)) {
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for_each_sg(data->sg, sg, data->sg_len, i) {
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if (sg->length & 0x3) {
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DBG("Reverting to PIO because of "
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"transfer size (%d)\n",
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sg->length);
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host->flags &= ~SDHCI_REQ_USE_DMA;
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break;
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}
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}
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}
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}
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/*
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* The assumption here being that alignment is the same after
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* translation to device address space.
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*/
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if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
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(host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
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(data->sg->offset & 0x3))) {
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DBG("Reverting to PIO because of bad alignment\n");
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host->flags &= ~SDHCI_REQ_USE_DMA;
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if (host->flags & SDHCI_REQ_USE_DMA) {
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int broken, i;
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struct scatterlist *sg;
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broken = 0;
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if (host->flags & SDHCI_USE_ADMA) {
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/*
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* As we use 3 byte chunks to work around
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* alignment problems, we need to check this
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* quirk.
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*/
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if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
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broken = 1;
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} else {
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if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
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broken = 1;
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}
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if (unlikely(broken)) {
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for_each_sg(data->sg, sg, data->sg_len, i) {
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if (sg->offset & 0x3) {
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DBG("Reverting to PIO because of "
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"bad alignment\n");
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host->flags &= ~SDHCI_REQ_USE_DMA;
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break;
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}
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}
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}
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}
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/*
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* Always adjust the DMA selection as some controllers
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* (e.g. JMicron) can't do PIO properly when the selection
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* is ADMA.
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*/
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if (host->version >= SDHCI_SPEC_200) {
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ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
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ctrl &= ~SDHCI_CTRL_DMA_MASK;
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if ((host->flags & SDHCI_REQ_USE_DMA) &&
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(host->flags & SDHCI_USE_ADMA))
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ctrl |= SDHCI_CTRL_ADMA32;
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else
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ctrl |= SDHCI_CTRL_SDMA;
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writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
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}
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if (host->flags & SDHCI_REQ_USE_DMA) {
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int count;
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if (host->flags & SDHCI_USE_ADMA) {
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sdhci_adma_table_pre(host, data);
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writel(host->adma_addr,
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host->ioaddr + SDHCI_ADMA_ADDRESS);
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} else {
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int count;
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count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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(data->flags & MMC_DATA_READ) ?
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DMA_FROM_DEVICE : DMA_TO_DEVICE);
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WARN_ON(count != 1);
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count = dma_map_sg(mmc_dev(host->mmc),
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data->sg, data->sg_len,
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(data->flags & MMC_DATA_READ) ?
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DMA_FROM_DEVICE :
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DMA_TO_DEVICE);
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WARN_ON(count != 1);
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writel(sg_dma_address(data->sg),
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host->ioaddr + SDHCI_DMA_ADDRESS);
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writel(sg_dma_address(data->sg),
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host->ioaddr + SDHCI_DMA_ADDRESS);
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}
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} else {
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host->cur_sg = data->sg;
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host->num_sg = data->sg_len;
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@ -457,9 +718,13 @@ static void sdhci_finish_data(struct sdhci_host *host)
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host->data = NULL;
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if (host->flags & SDHCI_REQ_USE_DMA) {
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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(data->flags & MMC_DATA_READ) ?
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DMA_FROM_DEVICE : DMA_TO_DEVICE);
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if (host->flags & SDHCI_USE_ADMA)
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sdhci_adma_table_post(host, data);
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else {
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dma_unmap_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, (data->flags & MMC_DATA_READ) ?
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DMA_FROM_DEVICE : DMA_TO_DEVICE);
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}
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}
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/*
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@ -1008,6 +1273,8 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
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host->data->error = -ETIMEDOUT;
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else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
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host->data->error = -EILSEQ;
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else if (intmask & SDHCI_INT_ADMA_ERROR)
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host->data->error = -EIO;
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if (host->data->error)
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sdhci_finish_data(host);
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@ -1199,7 +1466,6 @@ int sdhci_add_host(struct sdhci_host *host)
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{
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struct mmc_host *mmc;
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unsigned int caps;
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unsigned int version;
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int ret;
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WARN_ON(host == NULL);
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@ -1213,12 +1479,13 @@ int sdhci_add_host(struct sdhci_host *host)
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sdhci_reset(host, SDHCI_RESET_ALL);
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version = readw(host->ioaddr + SDHCI_HOST_VERSION);
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version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
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if (version > 1) {
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host->version = readw(host->ioaddr + SDHCI_HOST_VERSION);
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host->version = (host->version & SDHCI_SPEC_VER_MASK)
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>> SDHCI_SPEC_VER_SHIFT;
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if (host->version > SDHCI_SPEC_200) {
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printk(KERN_ERR "%s: Unknown controller version (%d). "
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"You may experience problems.\n", mmc_hostname(mmc),
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version);
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host->version);
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}
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caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
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@ -1236,17 +1503,47 @@ int sdhci_add_host(struct sdhci_host *host)
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host->flags &= ~SDHCI_USE_DMA;
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}
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if (host->flags & SDHCI_USE_DMA) {
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if ((host->version >= SDHCI_SPEC_200) &&
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(caps & SDHCI_CAN_DO_ADMA2))
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host->flags |= SDHCI_USE_ADMA;
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}
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if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
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(host->flags & SDHCI_USE_ADMA)) {
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DBG("Disabling ADMA as it is marked broken\n");
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host->flags &= ~SDHCI_USE_ADMA;
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}
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if (host->flags & SDHCI_USE_DMA) {
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if (host->ops->enable_dma) {
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if (host->ops->enable_dma(host)) {
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printk(KERN_WARNING "%s: No suitable DMA "
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"available. Falling back to PIO.\n",
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mmc_hostname(mmc));
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host->flags &= ~SDHCI_USE_DMA;
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host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
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}
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}
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}
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if (host->flags & SDHCI_USE_ADMA) {
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/*
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* We need to allocate descriptors for all sg entries
|
||||
* (128) and potentially one alignment transfer for
|
||||
* each of those entries.
|
||||
*/
|
||||
host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
|
||||
host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
|
||||
if (!host->adma_desc || !host->align_buffer) {
|
||||
kfree(host->adma_desc);
|
||||
kfree(host->align_buffer);
|
||||
printk(KERN_WARNING "%s: Unable to allocate ADMA "
|
||||
"buffers. Falling back to standard DMA.\n",
|
||||
mmc_hostname(mmc));
|
||||
host->flags &= ~SDHCI_USE_ADMA;
|
||||
}
|
||||
}
|
||||
|
||||
/* XXX: Hack to get MMC layer to avoid highmem */
|
||||
if (!(host->flags & SDHCI_USE_DMA))
|
||||
mmc_dev(host->mmc)->dma_mask = 0;
|
||||
@ -1298,13 +1595,16 @@ int sdhci_add_host(struct sdhci_host *host)
|
||||
spin_lock_init(&host->lock);
|
||||
|
||||
/*
|
||||
* Maximum number of segments. Hardware cannot do scatter lists.
|
||||
* Maximum number of segments. Depends on if the hardware
|
||||
* can do scatter/gather or not.
|
||||
*/
|
||||
if (host->flags & SDHCI_USE_DMA)
|
||||
if (host->flags & SDHCI_USE_ADMA)
|
||||
mmc->max_hw_segs = 128;
|
||||
else if (host->flags & SDHCI_USE_DMA)
|
||||
mmc->max_hw_segs = 1;
|
||||
else
|
||||
mmc->max_hw_segs = 16;
|
||||
mmc->max_phys_segs = 16;
|
||||
else /* PIO */
|
||||
mmc->max_hw_segs = 128;
|
||||
mmc->max_phys_segs = 128;
|
||||
|
||||
/*
|
||||
* Maximum number of sectors in one transfer. Limited by DMA boundary
|
||||
@ -1314,9 +1614,13 @@ int sdhci_add_host(struct sdhci_host *host)
|
||||
|
||||
/*
|
||||
* Maximum segment size. Could be one segment with the maximum number
|
||||
* of bytes.
|
||||
* of bytes. When doing hardware scatter/gather, each entry cannot
|
||||
* be larger than 64 KiB though.
|
||||
*/
|
||||
mmc->max_seg_size = mmc->max_req_size;
|
||||
if (host->flags & SDHCI_USE_ADMA)
|
||||
mmc->max_seg_size = 65536;
|
||||
else
|
||||
mmc->max_seg_size = mmc->max_req_size;
|
||||
|
||||
/*
|
||||
* Maximum block size. This varies from controller to controller and
|
||||
@ -1371,8 +1675,9 @@ int sdhci_add_host(struct sdhci_host *host)
|
||||
|
||||
mmc_add_host(mmc);
|
||||
|
||||
printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
|
||||
printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
|
||||
mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->bus_id,
|
||||
(host->flags & SDHCI_USE_ADMA)?"A":"",
|
||||
(host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
|
||||
|
||||
return 0;
|
||||
@ -1426,6 +1731,12 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
|
||||
|
||||
tasklet_kill(&host->card_tasklet);
|
||||
tasklet_kill(&host->finish_tasklet);
|
||||
|
||||
kfree(host->adma_desc);
|
||||
kfree(host->align_buffer);
|
||||
|
||||
host->adma_desc = NULL;
|
||||
host->align_buffer = NULL;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL_GPL(sdhci_remove_host);
|
||||
|
||||
@ -60,6 +60,11 @@
|
||||
#define SDHCI_CTRL_LED 0x01
|
||||
#define SDHCI_CTRL_4BITBUS 0x02
|
||||
#define SDHCI_CTRL_HISPD 0x04
|
||||
#define SDHCI_CTRL_DMA_MASK 0x18
|
||||
#define SDHCI_CTRL_SDMA 0x00
|
||||
#define SDHCI_CTRL_ADMA1 0x08
|
||||
#define SDHCI_CTRL_ADMA32 0x10
|
||||
#define SDHCI_CTRL_ADMA64 0x18
|
||||
|
||||
#define SDHCI_POWER_CONTROL 0x29
|
||||
#define SDHCI_POWER_ON 0x01
|
||||
@ -105,6 +110,7 @@
|
||||
#define SDHCI_INT_DATA_END_BIT 0x00400000
|
||||
#define SDHCI_INT_BUS_POWER 0x00800000
|
||||
#define SDHCI_INT_ACMD12ERR 0x01000000
|
||||
#define SDHCI_INT_ADMA_ERROR 0x02000000
|
||||
|
||||
#define SDHCI_INT_NORMAL_MASK 0x00007FFF
|
||||
#define SDHCI_INT_ERROR_MASK 0xFFFF8000
|
||||
@ -128,11 +134,14 @@
|
||||
#define SDHCI_CLOCK_BASE_SHIFT 8
|
||||
#define SDHCI_MAX_BLOCK_MASK 0x00030000
|
||||
#define SDHCI_MAX_BLOCK_SHIFT 16
|
||||
#define SDHCI_CAN_DO_ADMA2 0x00080000
|
||||
#define SDHCI_CAN_DO_ADMA1 0x00100000
|
||||
#define SDHCI_CAN_DO_HISPD 0x00200000
|
||||
#define SDHCI_CAN_DO_DMA 0x00400000
|
||||
#define SDHCI_CAN_VDD_330 0x01000000
|
||||
#define SDHCI_CAN_VDD_300 0x02000000
|
||||
#define SDHCI_CAN_VDD_180 0x04000000
|
||||
#define SDHCI_CAN_64BIT 0x10000000
|
||||
|
||||
/* 44-47 reserved for more caps */
|
||||
|
||||
@ -140,7 +149,16 @@
|
||||
|
||||
/* 4C-4F reserved for more max current */
|
||||
|
||||
/* 50-FB reserved */
|
||||
#define SDHCI_SET_ACMD12_ERROR 0x50
|
||||
#define SDHCI_SET_INT_ERROR 0x52
|
||||
|
||||
#define SDHCI_ADMA_ERROR 0x54
|
||||
|
||||
/* 55-57 reserved */
|
||||
|
||||
#define SDHCI_ADMA_ADDRESS 0x58
|
||||
|
||||
/* 60-FB reserved */
|
||||
|
||||
#define SDHCI_SLOT_INT_STATUS 0xFC
|
||||
|
||||
@ -149,6 +167,8 @@
|
||||
#define SDHCI_VENDOR_VER_SHIFT 8
|
||||
#define SDHCI_SPEC_VER_MASK 0x00FF
|
||||
#define SDHCI_SPEC_VER_SHIFT 0
|
||||
#define SDHCI_SPEC_100 0
|
||||
#define SDHCI_SPEC_200 1
|
||||
|
||||
struct sdhci_ops;
|
||||
|
||||
@ -170,16 +190,20 @@ struct sdhci_host {
|
||||
#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
|
||||
/* Controller has an unusable DMA engine */
|
||||
#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
|
||||
/* Controller has an unusable ADMA engine */
|
||||
#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
|
||||
/* Controller can only DMA from 32-bit aligned addresses */
|
||||
#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6)
|
||||
#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
|
||||
/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
|
||||
#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
|
||||
#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
|
||||
/* Controller can only ADMA chunks that are a multiple of 32 bits */
|
||||
#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
|
||||
/* Controller needs to be reset after each request to stay stable */
|
||||
#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8)
|
||||
#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
|
||||
/* Controller needs voltage and power writes to happen separately */
|
||||
#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<9)
|
||||
#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
|
||||
/* Controller provides an incorrect timeout value for transfers */
|
||||
#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<10)
|
||||
#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
|
||||
|
||||
int irq; /* Device IRQ */
|
||||
void __iomem * ioaddr; /* Mapped address */
|
||||
@ -197,8 +221,11 @@ struct sdhci_host {
|
||||
|
||||
int flags; /* Host attributes */
|
||||
#define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */
|
||||
#define SDHCI_REQ_USE_DMA (1<<1) /* Use DMA for this req. */
|
||||
#define SDHCI_DEVICE_DEAD (1<<2) /* Device unresponsive */
|
||||
#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
|
||||
#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
|
||||
#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
|
||||
|
||||
unsigned int version; /* SDHCI spec. version */
|
||||
|
||||
unsigned int max_clk; /* Max possible freq (MHz) */
|
||||
unsigned int timeout_clk; /* Timeout freq (KHz) */
|
||||
@ -216,6 +243,14 @@ struct sdhci_host {
|
||||
int offset; /* Offset into current sg */
|
||||
int remain; /* Bytes left in current */
|
||||
|
||||
int sg_count; /* Mapped sg entries */
|
||||
|
||||
u8 *adma_desc; /* ADMA descriptor table */
|
||||
u8 *align_buffer; /* Bounce buffer */
|
||||
|
||||
dma_addr_t adma_addr; /* Mapped ADMA descr. table */
|
||||
dma_addr_t align_addr; /* Mapped bounce buffer */
|
||||
|
||||
struct tasklet_struct card_tasklet; /* Tasklet structures */
|
||||
struct tasklet_struct finish_tasklet;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user