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gpio: tegra186: Support multiple interrupts per bank
Tegra194 and later support more than a single interrupt per bank. This is primarily useful for virtualization but can also be helpful for more fine-grained CPU affinity control. To keep things simple for now, route all pins to the first interrupt. For backwards-compatibility, support old device trees that specify only one interrupt per bank by counting the interrupts at probe time. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
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ca03874806
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@ -69,6 +69,8 @@ struct tegra_gpio_soc {
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const char *name;
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const char *name;
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unsigned int instance;
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unsigned int instance;
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unsigned int num_irqs_per_bank;
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const struct tegra186_pin_range *pin_ranges;
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const struct tegra186_pin_range *pin_ranges;
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unsigned int num_pin_ranges;
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unsigned int num_pin_ranges;
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const char *pinmux;
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const char *pinmux;
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@ -452,7 +454,7 @@ static void tegra186_gpio_irq(struct irq_desc *desc)
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struct irq_domain *domain = gpio->gpio.irq.domain;
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struct irq_domain *domain = gpio->gpio.irq.domain;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int parent = irq_desc_get_irq(desc);
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unsigned int parent = irq_desc_get_irq(desc);
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unsigned int i, offset = 0;
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unsigned int i, j, offset = 0;
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chained_irq_enter(chip, desc);
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chained_irq_enter(chip, desc);
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@ -465,7 +467,12 @@ static void tegra186_gpio_irq(struct irq_desc *desc)
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base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
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base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
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/* skip ports that are not associated with this bank */
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/* skip ports that are not associated with this bank */
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if (parent != gpio->irq[port->bank])
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for (j = 0; j < gpio->num_irqs_per_bank; j++) {
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if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
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break;
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}
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if (j == gpio->num_irqs_per_bank)
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goto skip;
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goto skip;
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value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
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value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
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@ -567,6 +574,7 @@ static const struct of_device_id tegra186_pmc_of_match[] = {
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static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
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static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
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{
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{
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struct device *dev = gpio->gpio.parent;
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unsigned int i, j;
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unsigned int i, j;
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u32 value;
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u32 value;
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@ -585,12 +593,30 @@ static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
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*/
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*/
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if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
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if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
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(value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
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(value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
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for (j = 0; j < 8; j++) {
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/*
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* On Tegra194 and later, each pin can be routed to one or more
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* interrupts.
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*/
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for (j = 0; j < gpio->num_irqs_per_bank; j++) {
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dev_dbg(dev, "programming default interrupt routing for port %s\n",
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port->name);
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offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
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offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
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value = readl(base + offset);
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/*
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value = BIT(port->pins) - 1;
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* By default we only want to route GPIO pins to IRQ 0. This works
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writel(value, base + offset);
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* only under the assumption that we're running as the host kernel
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* and hence all GPIO pins are owned by Linux.
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*
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* For cases where Linux is the guest OS, the hypervisor will have
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* to configure the interrupt routing and pass only the valid
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* interrupts via device tree.
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*/
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if (j == 0) {
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value = readl(base + offset);
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value = BIT(port->pins) - 1;
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writel(value, base + offset);
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}
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}
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}
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}
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}
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}
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}
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@ -610,6 +636,9 @@ static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
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gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
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gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
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if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
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goto error;
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return 0;
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return 0;
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error:
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error:
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@ -766,7 +795,8 @@ static int tegra186_gpio_probe(struct platform_device *pdev)
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irq->parents = gpio->irq;
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irq->parents = gpio->irq;
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}
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}
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tegra186_gpio_init_route_mapping(gpio);
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if (gpio->soc->num_irqs_per_bank > 1)
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tegra186_gpio_init_route_mapping(gpio);
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np = of_find_matching_node(NULL, tegra186_pmc_of_match);
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np = of_find_matching_node(NULL, tegra186_pmc_of_match);
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if (np) {
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if (np) {
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@ -833,6 +863,7 @@ static const struct tegra_gpio_soc tegra186_main_soc = {
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.ports = tegra186_main_ports,
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.ports = tegra186_main_ports,
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.name = "tegra186-gpio",
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.name = "tegra186-gpio",
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.instance = 0,
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.instance = 0,
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.num_irqs_per_bank = 1,
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};
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};
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#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
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#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
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@ -859,6 +890,7 @@ static const struct tegra_gpio_soc tegra186_aon_soc = {
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.ports = tegra186_aon_ports,
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.ports = tegra186_aon_ports,
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.name = "tegra186-gpio-aon",
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.name = "tegra186-gpio-aon",
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.instance = 1,
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.instance = 1,
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.num_irqs_per_bank = 1,
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};
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};
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#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
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#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
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@ -910,6 +942,7 @@ static const struct tegra_gpio_soc tegra194_main_soc = {
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.ports = tegra194_main_ports,
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.ports = tegra194_main_ports,
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.name = "tegra194-gpio",
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.name = "tegra194-gpio",
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.instance = 0,
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.instance = 0,
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.num_irqs_per_bank = 8,
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.num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
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.num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
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.pin_ranges = tegra194_main_pin_ranges,
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.pin_ranges = tegra194_main_pin_ranges,
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.pinmux = "nvidia,tegra194-pinmux",
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.pinmux = "nvidia,tegra194-pinmux",
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@ -936,6 +969,7 @@ static const struct tegra_gpio_soc tegra194_aon_soc = {
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.ports = tegra194_aon_ports,
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.ports = tegra194_aon_ports,
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.name = "tegra194-gpio-aon",
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.name = "tegra194-gpio-aon",
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.instance = 1,
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.instance = 1,
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.num_irqs_per_bank = 8,
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};
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};
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static const struct of_device_id tegra186_gpio_of_match[] = {
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static const struct of_device_id tegra186_gpio_of_match[] = {
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