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https://github.com/edk2-porting/linux-next.git
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Merge branch 'x86/uv' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86/uv' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: UV BAU distribution and payload MMRs x86: UV: BAU partition-relative distribution map x86, uv: add Kconfig dependency on NUMA for UV systems x86: prevent /sys/firmware/sgi_uv from being created on non-uv systems x86, UV: Fix for nodes with memory and no cpus x86, UV: system table in bios accessed after unmap x86: UV BAU messaging timeouts x86: UV BAU and nodes with no memory
This commit is contained in:
Linus Torvalds
commit
20d9207849
@ -353,6 +353,7 @@ config X86_UV
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bool "SGI Ultraviolet"
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depends on X86_64
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depends on X86_EXTENDED_PLATFORM
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depends on NUMA
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select X86_X2APIC
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---help---
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This option is needed in order to support SGI Ultraviolet systems.
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@ -17,6 +17,11 @@
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/* ========================================================================= */
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/* UVH_BAU_DATA_CONFIG */
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/* ========================================================================= */
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#define UVH_LB_BAU_MISC_CONTROL 0x320170UL
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#define UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT 15
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#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT 16
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#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 0x000000000bUL
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/* 1011 timebase 7 (168millisec) * 3 ticks -> 500ms */
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#define UVH_BAU_DATA_CONFIG 0x61680UL
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#define UVH_BAU_DATA_CONFIG_32 0x0438
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@ -549,7 +549,8 @@ void __init uv_system_init(void)
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unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
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int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
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int max_pnode = 0;
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unsigned long mmr_base, present;
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unsigned long mmr_base, present, paddr;
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unsigned short pnode_mask;
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map_low_mmrs();
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@ -592,6 +593,7 @@ void __init uv_system_init(void)
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}
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}
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pnode_mask = (1 << n_val) - 1;
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node_id.v = uv_read_local_mmr(UVH_NODE_ID);
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gnode_upper = (((unsigned long)node_id.s.node_id) &
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~((1 << n_val) - 1)) << m_val;
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@ -615,7 +617,7 @@ void __init uv_system_init(void)
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uv_cpu_hub_info(cpu)->numa_blade_id = blade;
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uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
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uv_cpu_hub_info(cpu)->pnode = pnode;
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uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
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uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
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uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
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uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
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uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
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@ -631,6 +633,16 @@ void __init uv_system_init(void)
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lcpu, blade);
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}
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/* Add blade/pnode info for nodes without cpus */
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for_each_online_node(nid) {
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if (uv_node_to_blade[nid] >= 0)
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continue;
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paddr = node_start_pfn(nid) << PAGE_SHIFT;
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pnode = (paddr >> m_val) & pnode_mask;
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blade = boot_pnode_to_blade(pnode);
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uv_node_to_blade[nid] = blade;
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}
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map_gru_high(max_pnode);
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map_mmr_high(max_pnode);
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map_config_high(max_pnode);
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@ -182,7 +182,8 @@ void uv_bios_init(void)
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memcpy(&uv_systab, tab, sizeof(struct uv_systab));
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iounmap(tab);
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printk(KERN_INFO "EFI UV System Table Revision %d\n", tab->revision);
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printk(KERN_INFO "EFI UV System Table Revision %d\n",
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uv_systab.revision);
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}
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#else /* !CONFIG_EFI */
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@ -25,12 +25,42 @@ static int uv_bau_retry_limit __read_mostly;
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/* position of pnode (which is nasid>>1): */
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static int uv_nshift __read_mostly;
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/* base pnode in this partition */
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static int uv_partition_base_pnode __read_mostly;
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static unsigned long uv_mmask __read_mostly;
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static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
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static DEFINE_PER_CPU(struct bau_control, bau_control);
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/*
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* Determine the first node on a blade.
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*/
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static int __init blade_to_first_node(int blade)
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{
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int node, b;
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for_each_online_node(node) {
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b = uv_node_to_blade_id(node);
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if (blade == b)
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return node;
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}
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return -1; /* shouldn't happen */
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}
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/*
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* Determine the apicid of the first cpu on a blade.
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*/
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static int __init blade_to_first_apicid(int blade)
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{
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int cpu;
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for_each_present_cpu(cpu)
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if (blade == uv_cpu_to_blade_id(cpu))
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return per_cpu(x86_cpu_to_apicid, cpu);
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return -1;
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}
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/*
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* Free a software acknowledge hardware resource by clearing its Pending
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* bit. This will return a reply to the sender.
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@ -67,7 +97,7 @@ static void uv_bau_process_message(struct bau_payload_queue_entry *msg,
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msp = __get_cpu_var(bau_control).msg_statuses + msg_slot;
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cpu = uv_blade_processor_id();
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msg->number_of_cpus =
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uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id()));
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uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id()));
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this_cpu_mask = 1UL << cpu;
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if (msp->seen_by.bits & this_cpu_mask)
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return;
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@ -215,14 +245,14 @@ static int uv_wait_completion(struct bau_desc *bau_desc,
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* Returns @flush_mask if some remote flushing remains to be done. The
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* mask will have some bits still set.
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*/
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const struct cpumask *uv_flush_send_and_wait(int cpu, int this_blade,
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const struct cpumask *uv_flush_send_and_wait(int cpu, int this_pnode,
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struct bau_desc *bau_desc,
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struct cpumask *flush_mask)
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{
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int completion_status = 0;
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int right_shift;
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int tries = 0;
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int blade;
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int pnode;
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int bit;
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unsigned long mmr_offset;
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unsigned long index;
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@ -265,8 +295,8 @@ const struct cpumask *uv_flush_send_and_wait(int cpu, int this_blade,
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* use the IPI method of shootdown on them.
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*/
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for_each_cpu(bit, flush_mask) {
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blade = uv_cpu_to_blade_id(bit);
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if (blade == this_blade)
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pnode = uv_cpu_to_pnode(bit);
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if (pnode == this_pnode)
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continue;
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cpumask_clear_cpu(bit, flush_mask);
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}
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@ -309,16 +339,16 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
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struct cpumask *flush_mask = __get_cpu_var(uv_flush_tlb_mask);
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int i;
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int bit;
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int blade;
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int pnode;
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int uv_cpu;
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int this_blade;
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int this_pnode;
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int locals = 0;
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struct bau_desc *bau_desc;
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cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
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uv_cpu = uv_blade_processor_id();
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this_blade = uv_numa_blade_id();
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this_pnode = uv_hub_info->pnode;
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bau_desc = __get_cpu_var(bau_control).descriptor_base;
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bau_desc += UV_ITEMS_PER_DESCRIPTOR * uv_cpu;
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@ -326,13 +356,14 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
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i = 0;
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for_each_cpu(bit, flush_mask) {
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blade = uv_cpu_to_blade_id(bit);
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BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1));
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if (blade == this_blade) {
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pnode = uv_cpu_to_pnode(bit);
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BUG_ON(pnode > (UV_DISTRIBUTION_SIZE - 1));
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if (pnode == this_pnode) {
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locals++;
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continue;
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}
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bau_node_set(blade, &bau_desc->distribution);
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bau_node_set(pnode - uv_partition_base_pnode,
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&bau_desc->distribution);
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i++;
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}
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if (i == 0) {
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@ -350,7 +381,7 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
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bau_desc->payload.address = va;
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bau_desc->payload.sending_cpu = cpu;
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return uv_flush_send_and_wait(uv_cpu, this_blade, bau_desc, flush_mask);
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return uv_flush_send_and_wait(uv_cpu, this_pnode, bau_desc, flush_mask);
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}
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/*
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@ -418,24 +449,58 @@ void uv_bau_message_interrupt(struct pt_regs *regs)
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set_irq_regs(old_regs);
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}
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/*
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* uv_enable_timeouts
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*
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* Each target blade (i.e. blades that have cpu's) needs to have
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* shootdown message timeouts enabled. The timeout does not cause
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* an interrupt, but causes an error message to be returned to
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* the sender.
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*/
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static void uv_enable_timeouts(void)
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{
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int i;
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int blade;
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int last_blade;
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int nblades;
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int pnode;
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int cur_cpu = 0;
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unsigned long apicid;
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unsigned long mmr_image;
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last_blade = -1;
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for_each_online_node(i) {
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blade = uv_node_to_blade_id(i);
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if (blade == last_blade)
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nblades = uv_num_possible_blades();
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for (blade = 0; blade < nblades; blade++) {
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if (!uv_blade_nr_possible_cpus(blade))
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continue;
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last_blade = blade;
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apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
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pnode = uv_blade_to_pnode(blade);
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cur_cpu += uv_blade_nr_possible_cpus(i);
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mmr_image =
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uv_read_global_mmr64(pnode, UVH_LB_BAU_MISC_CONTROL);
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/*
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* Set the timeout period and then lock it in, in three
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* steps; captures and locks in the period.
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*
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* To program the period, the SOFT_ACK_MODE must be off.
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*/
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mmr_image &= ~((unsigned long)1 <<
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UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT);
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uv_write_global_mmr64
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(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
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/*
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* Set the 4-bit period.
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*/
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mmr_image &= ~((unsigned long)0xf <<
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UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT);
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mmr_image |= (UV_INTD_SOFT_ACK_TIMEOUT_PERIOD <<
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UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT);
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uv_write_global_mmr64
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(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
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/*
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* Subsequent reversals of the timebase bit (3) cause an
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* immediate timeout of one or all INTD resources as
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* indicated in bits 2:0 (7 causes all of them to timeout).
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*/
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mmr_image |= ((unsigned long)1 <<
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UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT);
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uv_write_global_mmr64
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(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
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}
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}
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@ -482,8 +547,7 @@ static int uv_ptc_seq_show(struct seq_file *file, void *data)
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stat->requestee, stat->onetlb, stat->alltlb,
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stat->s_retry, stat->d_retry, stat->ptc_i);
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seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n",
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uv_read_global_mmr64(uv_blade_to_pnode
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(uv_cpu_to_blade_id(cpu)),
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uv_read_global_mmr64(uv_cpu_to_pnode(cpu),
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UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
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stat->sflush, stat->dflush,
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stat->retriesok, stat->nomsg,
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@ -617,16 +681,18 @@ static struct bau_control * __init uv_table_bases_init(int blade, int node)
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* finish the initialization of the per-blade control structures
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*/
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static void __init
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uv_table_bases_finish(int blade, int node, int cur_cpu,
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uv_table_bases_finish(int blade,
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struct bau_control *bau_tablesp,
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struct bau_desc *adp)
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{
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struct bau_control *bcp;
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int i;
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int cpu;
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for (i = cur_cpu; i < cur_cpu + uv_blade_nr_possible_cpus(blade); i++) {
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bcp = (struct bau_control *)&per_cpu(bau_control, i);
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for_each_present_cpu(cpu) {
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if (blade != uv_cpu_to_blade_id(cpu))
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continue;
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bcp = (struct bau_control *)&per_cpu(bau_control, cpu);
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bcp->bau_msg_head = bau_tablesp->va_queue_first;
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bcp->va_queue_first = bau_tablesp->va_queue_first;
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bcp->va_queue_last = bau_tablesp->va_queue_last;
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@ -649,11 +715,10 @@ uv_activation_descriptor_init(int node, int pnode)
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struct bau_desc *adp;
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struct bau_desc *ad2;
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adp = (struct bau_desc *)
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kmalloc_node(16384, GFP_KERNEL, node);
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adp = (struct bau_desc *)kmalloc_node(16384, GFP_KERNEL, node);
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BUG_ON(!adp);
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pa = __pa((unsigned long)adp);
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pa = uv_gpa(adp); /* need the real nasid*/
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n = pa >> uv_nshift;
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m = pa & uv_mmask;
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@ -667,8 +732,12 @@ uv_activation_descriptor_init(int node, int pnode)
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for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) {
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memset(ad2, 0, sizeof(struct bau_desc));
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ad2->header.sw_ack_flag = 1;
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ad2->header.base_dest_nodeid =
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uv_blade_to_pnode(uv_cpu_to_blade_id(0));
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/*
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* base_dest_nodeid is the first node in the partition, so
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* the bit map will indicate partition-relative node numbers.
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* note that base_dest_nodeid is actually a nasid.
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*/
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ad2->header.base_dest_nodeid = uv_partition_base_pnode << 1;
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ad2->header.command = UV_NET_ENDPOINT_INTD;
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ad2->header.int_both = 1;
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/*
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@ -686,6 +755,8 @@ static struct bau_payload_queue_entry * __init
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uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp)
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{
|
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struct bau_payload_queue_entry *pqp;
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unsigned long pa;
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int pn;
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char *cp;
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pqp = (struct bau_payload_queue_entry *) kmalloc_node(
|
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@ -696,10 +767,14 @@ uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp)
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cp = (char *)pqp + 31;
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pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
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bau_tablesp->va_queue_first = pqp;
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/*
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* need the pnode of where the memory was really allocated
|
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*/
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pa = uv_gpa(pqp);
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pn = pa >> uv_nshift;
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uv_write_global_mmr64(pnode,
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UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
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((unsigned long)pnode <<
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UV_PAYLOADQ_PNODE_SHIFT) |
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((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) |
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uv_physnodeaddr(pqp));
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uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
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uv_physnodeaddr(pqp));
|
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@ -715,8 +790,9 @@ uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp)
|
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/*
|
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* Initialization of each UV blade's structures
|
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*/
|
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static int __init uv_init_blade(int blade, int node, int cur_cpu)
|
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static int __init uv_init_blade(int blade)
|
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{
|
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int node;
|
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int pnode;
|
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unsigned long pa;
|
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unsigned long apicid;
|
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@ -724,16 +800,17 @@ static int __init uv_init_blade(int blade, int node, int cur_cpu)
|
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struct bau_payload_queue_entry *pqp;
|
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struct bau_control *bau_tablesp;
|
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node = blade_to_first_node(blade);
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bau_tablesp = uv_table_bases_init(blade, node);
|
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pnode = uv_blade_to_pnode(blade);
|
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adp = uv_activation_descriptor_init(node, pnode);
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pqp = uv_payload_queue_init(node, pnode, bau_tablesp);
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uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp);
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uv_table_bases_finish(blade, bau_tablesp, adp);
|
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/*
|
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* the below initialization can't be in firmware because the
|
||||
* messaging IRQ will be determined by the OS
|
||||
*/
|
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apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
|
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apicid = blade_to_first_apicid(blade);
|
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pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG);
|
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if ((pa & 0xff) != UV_BAU_MESSAGE) {
|
||||
uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
|
||||
@ -748,9 +825,7 @@ static int __init uv_init_blade(int blade, int node, int cur_cpu)
|
||||
static int __init uv_bau_init(void)
|
||||
{
|
||||
int blade;
|
||||
int node;
|
||||
int nblades;
|
||||
int last_blade;
|
||||
int cur_cpu;
|
||||
|
||||
if (!is_uv_system())
|
||||
@ -763,29 +838,21 @@ static int __init uv_bau_init(void)
|
||||
uv_bau_retry_limit = 1;
|
||||
uv_nshift = uv_hub_info->n_val;
|
||||
uv_mmask = (1UL << uv_hub_info->n_val) - 1;
|
||||
nblades = 0;
|
||||
last_blade = -1;
|
||||
cur_cpu = 0;
|
||||
for_each_online_node(node) {
|
||||
blade = uv_node_to_blade_id(node);
|
||||
if (blade == last_blade)
|
||||
continue;
|
||||
last_blade = blade;
|
||||
nblades++;
|
||||
}
|
||||
nblades = uv_num_possible_blades();
|
||||
|
||||
uv_bau_table_bases = (struct bau_control **)
|
||||
kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL);
|
||||
BUG_ON(!uv_bau_table_bases);
|
||||
|
||||
last_blade = -1;
|
||||
for_each_online_node(node) {
|
||||
blade = uv_node_to_blade_id(node);
|
||||
if (blade == last_blade)
|
||||
continue;
|
||||
last_blade = blade;
|
||||
uv_init_blade(blade, node, cur_cpu);
|
||||
cur_cpu += uv_blade_nr_possible_cpus(blade);
|
||||
}
|
||||
uv_partition_base_pnode = 0x7fffffff;
|
||||
for (blade = 0; blade < nblades; blade++)
|
||||
if (uv_blade_nr_possible_cpus(blade) &&
|
||||
(uv_blade_to_pnode(blade) < uv_partition_base_pnode))
|
||||
uv_partition_base_pnode = uv_blade_to_pnode(blade);
|
||||
for (blade = 0; blade < nblades; blade++)
|
||||
if (uv_blade_nr_possible_cpus(blade))
|
||||
uv_init_blade(blade);
|
||||
|
||||
alloc_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);
|
||||
uv_enable_timeouts();
|
||||
|
||||
|
||||
@ -21,6 +21,7 @@
|
||||
|
||||
#include <linux/sysdev.h>
|
||||
#include <asm/uv/bios.h>
|
||||
#include <asm/uv/uv.h>
|
||||
|
||||
struct kobject *sgi_uv_kobj;
|
||||
|
||||
@ -47,6 +48,9 @@ static int __init sgi_uv_sysfs_init(void)
|
||||
{
|
||||
unsigned long ret;
|
||||
|
||||
if (!is_uv_system())
|
||||
return -ENODEV;
|
||||
|
||||
if (!sgi_uv_kobj)
|
||||
sgi_uv_kobj = kobject_create_and_add("sgi_uv", firmware_kobj);
|
||||
if (!sgi_uv_kobj) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user