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nvme: move ctrl cap to struct nvme_ctrl
All transports use either a private cache of controller cap or an on-stack copy, move it to the generic struct nvme_ctrl. In the future it will also be maintained by the core. Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Reviewed-by: Max Gurtovoy <maxg@mellanox.com> Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
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@ -152,8 +152,6 @@ struct nvme_fc_ctrl {
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u64 association_id;
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u64 cap;
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struct list_head ctrl_list; /* rport->ctrl_list */
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struct blk_mq_tag_set admin_tag_set;
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@ -2328,7 +2326,7 @@ nvme_fc_create_association(struct nvme_fc_ctrl *ctrl)
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* prior connection values
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*/
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ret = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->cap);
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ret = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->ctrl.cap);
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if (ret) {
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dev_err(ctrl->ctrl.device,
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"prop_get NVME_REG_CAP failed\n");
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@ -2336,9 +2334,9 @@ nvme_fc_create_association(struct nvme_fc_ctrl *ctrl)
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}
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ctrl->ctrl.sqsize =
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min_t(int, NVME_CAP_MQES(ctrl->cap) + 1, ctrl->ctrl.sqsize);
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min_t(int, NVME_CAP_MQES(ctrl->ctrl.cap) + 1, ctrl->ctrl.sqsize);
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ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap);
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ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->ctrl.cap);
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if (ret)
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goto out_disconnect_admin_queue;
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@ -144,6 +144,7 @@ struct nvme_ctrl {
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u32 ctrl_config;
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u32 queue_count;
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u64 cap;
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u32 page_size;
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u32 max_hw_sectors;
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u16 oncs;
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@ -1144,8 +1144,7 @@ static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
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if (shutdown)
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nvme_shutdown_ctrl(&dev->ctrl);
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else
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nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
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dev->bar + NVME_REG_CAP));
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nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
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spin_lock_irq(&nvmeq->q_lock);
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nvme_process_cq(nvmeq);
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@ -1388,7 +1387,6 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
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{
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int result;
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u32 aqa;
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u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
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struct nvme_queue *nvmeq;
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result = nvme_remap_bar(dev, db_bar_size(dev, 0));
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@ -1396,13 +1394,13 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
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return result;
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dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
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NVME_CAP_NSSRC(cap) : 0;
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NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
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if (dev->subsystem &&
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(readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
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writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
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result = nvme_disable_ctrl(&dev->ctrl, cap);
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result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
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if (result < 0)
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return result;
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@ -1421,7 +1419,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
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lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
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lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
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result = nvme_enable_ctrl(&dev->ctrl, cap);
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result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
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if (result)
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return result;
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@ -1865,7 +1863,6 @@ static int nvme_dev_add(struct nvme_dev *dev)
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static int nvme_pci_enable(struct nvme_dev *dev)
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{
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u64 cap;
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int result = -ENOMEM;
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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@ -1892,10 +1889,11 @@ static int nvme_pci_enable(struct nvme_dev *dev)
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if (result < 0)
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return result;
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cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
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dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
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dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
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dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
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dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
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NVME_Q_DEPTH);
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dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
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dev->dbs = dev->bar + 4096;
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/*
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@ -1909,7 +1907,7 @@ static int nvme_pci_enable(struct nvme_dev *dev)
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dev->q_depth);
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} else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
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(pdev->device == 0xa821 || pdev->device == 0xa822) &&
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NVME_CAP_MQES(cap) == 0) {
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NVME_CAP_MQES(dev->ctrl.cap) == 0) {
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dev->q_depth = 64;
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dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
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"set queue depth=%u\n", dev->q_depth);
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@ -118,7 +118,6 @@ struct nvme_rdma_ctrl {
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struct blk_mq_tag_set admin_tag_set;
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struct nvme_rdma_device *device;
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u64 cap;
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u32 max_fr_pages;
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struct sockaddr_storage addr;
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@ -728,7 +727,7 @@ static void nvme_rdma_reconnect_ctrl_work(struct work_struct *work)
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set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[0].flags);
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ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap);
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ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->ctrl.cap);
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if (ret)
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goto requeue;
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@ -1573,7 +1572,8 @@ static int nvme_rdma_configure_admin_queue(struct nvme_rdma_ctrl *ctrl)
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set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[0].flags);
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error = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->cap);
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error = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP,
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&ctrl->ctrl.cap);
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if (error) {
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dev_err(ctrl->ctrl.device,
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"prop_get NVME_REG_CAP failed\n");
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@ -1581,9 +1581,9 @@ static int nvme_rdma_configure_admin_queue(struct nvme_rdma_ctrl *ctrl)
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}
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ctrl->ctrl.sqsize =
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min_t(int, NVME_CAP_MQES(ctrl->cap), ctrl->ctrl.sqsize);
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min_t(int, NVME_CAP_MQES(ctrl->ctrl.cap), ctrl->ctrl.sqsize);
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error = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap);
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error = nvme_enable_ctrl(&ctrl->ctrl, ctrl->ctrl.cap);
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if (error)
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goto out_cleanup_queue;
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@ -48,7 +48,6 @@ struct nvme_loop_ctrl {
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struct blk_mq_tag_set admin_tag_set;
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struct list_head list;
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u64 cap;
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struct blk_mq_tag_set tag_set;
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struct nvme_loop_iod async_event_iod;
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struct nvme_ctrl ctrl;
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@ -387,7 +386,7 @@ static int nvme_loop_configure_admin_queue(struct nvme_loop_ctrl *ctrl)
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if (error)
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goto out_cleanup_queue;
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error = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->cap);
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error = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->ctrl.cap);
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if (error) {
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dev_err(ctrl->ctrl.device,
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"prop_get NVME_REG_CAP failed\n");
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@ -395,9 +394,9 @@ static int nvme_loop_configure_admin_queue(struct nvme_loop_ctrl *ctrl)
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}
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ctrl->ctrl.sqsize =
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min_t(int, NVME_CAP_MQES(ctrl->cap), ctrl->ctrl.sqsize);
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min_t(int, NVME_CAP_MQES(ctrl->ctrl.cap), ctrl->ctrl.sqsize);
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error = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap);
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error = nvme_enable_ctrl(&ctrl->ctrl, ctrl->ctrl.cap);
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if (error)
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goto out_cleanup_queue;
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