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clk: si5351: fix .round_rate for multisynth 6-7
The divider calculation for multisynth 6 and 7 differs from the calculation for multisynth 0-5. For MS6 and MS7, set MSx_P1 directly, MSx_P1=divide value [AN619, p. 6]. Referenced document: [AN619] Manually Generating an Si5351 Register Map, Rev. 0.4 Signed-off-by: Sergej Sawazki <ce3a@gmx.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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@ -552,7 +552,8 @@ static const struct clk_ops si5351_pll_ops = {
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* MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
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* MSx_P3[19:0] = c
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*
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* MS[6,7] are integer (P1) divide only, P2 = 0, P3 = 0
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* MS[6,7] are integer (P1) divide only, P1 = divide value,
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* P2 and P3 are not applicable
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*
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* for 150MHz < fOUT <= 160MHz:
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*
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@ -679,6 +680,16 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
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c = 1;
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*parent_rate = a * rate;
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} else if (hwdata->num >= 6) {
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/* determine the closest integer divider */
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a = DIV_ROUND_CLOSEST(*parent_rate, rate);
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if (a < SI5351_MULTISYNTH_A_MIN)
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a = SI5351_MULTISYNTH_A_MIN;
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if (a > SI5351_MULTISYNTH67_A_MAX)
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a = SI5351_MULTISYNTH67_A_MAX;
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b = 0;
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c = 1;
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} else {
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unsigned long rfrac, denom;
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@ -692,9 +703,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
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a = *parent_rate / rate;
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if (a < SI5351_MULTISYNTH_A_MIN)
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a = SI5351_MULTISYNTH_A_MIN;
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if (hwdata->num >= 6 && a > SI5351_MULTISYNTH67_A_MAX)
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a = SI5351_MULTISYNTH67_A_MAX;
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else if (a > SI5351_MULTISYNTH_A_MAX)
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if (a > SI5351_MULTISYNTH_A_MAX)
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a = SI5351_MULTISYNTH_A_MAX;
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/* find best approximation for b/c = fVCO mod fOUT */
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@ -723,6 +732,10 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
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hwdata->params.p3 = 1;
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hwdata->params.p2 = 0;
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hwdata->params.p1 = 0;
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} else if (hwdata->num >= 6) {
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hwdata->params.p3 = 0;
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hwdata->params.p2 = 0;
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hwdata->params.p1 = a;
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} else {
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hwdata->params.p3 = c;
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hwdata->params.p2 = (128 * b) % c;
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