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Samsung DTS ARM changes for v5.2

Browse Source 
1. Use proper ADC on Exynos4412.
 2. Extend the Exynos5420 Arndale Octa board with: CPU cooling maps,
    unused regulators, ADC and UHS-I SD card support.  Beside that adjust
    regulators to proper level and add always-on when needed.
 3. Extend the Exynos5260: high speed I2C and proper external interrupts.
    Also fix shared external interrupt line and use better PLL for MMC
    clocks.
 4. Fix audio recording (broken around v5.1) and microphone recording
    (since v4.14) on Exynos5422 Odroid XU3 boards.
 5. Minor cleanups (stdout-path and bootargs).
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Merge tag 'samsung-dt-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM changes for v5.2

1. Use proper ADC on Exynos4412.
2. Extend the Exynos5420 Arndale Octa board with: CPU cooling maps,
   unused regulators, ADC and UHS-I SD card support.  Beside that adjust
   regulators to proper level and add always-on when needed.
3. Extend the Exynos5260: high speed I2C and proper external interrupts.
   Also fix shared external interrupt line and use better PLL for MMC
   clocks.
4. Fix audio recording (broken around v5.1) and microphone recording
   (since v4.14) on Exynos5422 Odroid XU3 boards.
5. Minor cleanups (stdout-path and bootargs).

* tag 'samsung-dt-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: Remove console argument from bootargs
  ARM: dts: exynos: Use stdout-path property instead of console in bootargs
  ARM: dts: exynos: Fix spelling mistake of EXYNOS5420
  ARM: dts: exynos: Fix audio (microphone) routing on Odroid XU3
  ARM: dts: exynos: Always enable necessary APIO_1V8 and ABB_1V8 regulators on Arndale Octa
  ARM: dts: exynos: Extend the eMMC node on Arndale Octa
  ARM: dts: exynos: Add support for UHS-I SD cards on Arndale Octa
  ARM: dts: exynos: Adjust ldo23 and ldo27 to lower levels on Arndale Octa
  ARM: dts: exynos: Fix audio routing on Odroid XU3
  ARM: dts: exynos: Enable ADC on Arndale Octa
  ARM: dts: exynos: Fix interrupt for shared EINTs on Exynos5260
  ARM: dts: exynos: Add interrupts for dedicated EINTs on Exynos5260
  ARM: dts: exynos: Add high speed I2C ports for Exynos5260
  ARM: dts: exynos: Use bustop PLL as the source for MMC clocks on Exynos5260
  ARM: dts: exynos: Order nodes alphabetically in Arndale Octa
  ARM: dts: exynos: Add CPU cooling on Arndale Octa
  ARM: dts: exynos: Add unused PMIC regulators on Arndale Octa board
  ARM: dts: exynos: Use stdout path property on Arndale Octa board
  ARM: dts: exynos: Document regulator used by ADC on Odroid U3
  ARM: dts: exynos: Use ADC for Exynos4x12 on Exynos4412

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-04-28 12:29:20 -07:00
commit 1fbdc24775
18 changed files with 477 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/exynos4210-origen.dts
View File

@ -30,8 +30,8 @@
};
chosen {
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
stdout-path = &serial_2;
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
stdout-path = "serial2:115200n8";
};
mmc_reg: voltage-regulator {

4
arch/arm/boot/dts/exynos4210-smdkv310.dts
View File

@ -26,8 +26,8 @@
};
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
stdout-path = &serial_1;
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
stdout-path = "serial1:115200n8";
};
fixed-rate-clocks {

4
arch/arm/boot/dts/exynos4210-trats.dts
View File

@ -26,8 +26,8 @@
};
chosen {
bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
stdout-path = &serial_2;
bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
stdout-path = "serial2:115200n8";
};
regulators {

4
arch/arm/boot/dts/exynos4210-universal_c210.dts
View File

@ -24,8 +24,8 @@
};
chosen {
bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
stdout-path = &serial_2;
bootargs = "root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
stdout-path = "serial2:115200n8";
};

5
arch/arm/boot/dts/exynos4412-odroidu3.dts
View File

@ -66,6 +66,11 @@
};
};
&adc {
vdd-supply = <&ldo10_reg>;
/* Nothing connected to ADC inputs, keep it disabled */
};
/* Supply for LAN9730/SMSC95xx */
&buck8_reg {
regulator-name = "BUCK8_P3V3";

3
arch/arm/boot/dts/exynos4412-origen.dts
View File

@ -25,8 +25,7 @@
};
chosen {
bootargs ="console=ttySAC2,115200";
stdout-path = &serial_2;
stdout-path = "serial2:115200n8";
};
firmware@203f000 {

4
arch/arm/boot/dts/exynos4412-smdk4412.dts
View File

@ -23,8 +23,8 @@
};
chosen {
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
stdout-path = &serial_1;
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
stdout-path = "serial1:115200n8";
};
fixed-rate-clocks {

3
arch/arm/boot/dts/exynos4412-trats2.dts
View File

@ -22,6 +22,7 @@
};
chosen {
bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
stdout-path = "serial2:115200n8";
};
};

2
arch/arm/boot/dts/exynos4412.dtsi
View File

@ -274,7 +274,7 @@
};
adc: adc@126c0000 {
compatible = "samsung,exynos-adc-v1";
compatible = "samsung,exynos4212-adc";
reg = <0x126C0000 0x100>;
interrupt-parent = <&combiner>;
interrupts = <10 3>;

3
arch/arm/boot/dts/exynos5250-smdk5250.dts
View File

@ -24,7 +24,8 @@
};
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
stdout-path = "serial2:115200n8";
};
vdd: fixed-regulator-vdd {

16
arch/arm/boot/dts/exynos5260-pinctrl.dtsi
View File

@ -153,6 +153,14 @@
#gpio-cells = <2>;
interrupt-controller;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@ -161,6 +169,14 @@
#gpio-cells = <2>;
interrupt-controller;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};

2
arch/arm/boot/dts/exynos5260-xyref5260.dts
View File

@ -19,7 +19,7 @@
};
chosen {
bootargs = "console=ttySAC2,115200";
stdout-path = "serial2:115200n8";
};
fin_pll: xxti {

82
arch/arm/boot/dts/exynos5260.dtsi
View File

@ -17,6 +17,10 @@
#size-cells = <1>;
aliases {
i2c0 = &hsi2c_0;
i2c1 = &hsi2c_1;
i2c2 = &hsi2c_2;
i2c3 = &hsi2c_3;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@ -223,7 +227,7 @@
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
};
@ -288,6 +292,14 @@
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
clock-names = "biu", "ciu";
assigned-clocks =
<&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>,
<&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>,
<&clock_top TOP_SCLK_MMC0>;
assigned-clock-parents =
<&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
<&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>;
assigned-clock-rates = <0>, <0>, <800000000>;
fifo-depth = <64>;
status = "disabled";
};
@ -300,6 +312,14 @@
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
clock-names = "biu", "ciu";
assigned-clocks =
<&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>,
<&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>,
<&clock_top TOP_SCLK_MMC1>;
assigned-clock-parents =
<&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
<&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>;
assigned-clock-rates = <0>, <0>, <800000000>;
fifo-depth = <64>;
status = "disabled";
};
@ -312,9 +332,69 @@
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
clock-names = "biu", "ciu";
assigned-clocks =
<&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>,
<&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>,
<&clock_top TOP_SCLK_MMC2>;
assigned-clock-parents =
<&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
<&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>;
assigned-clock-rates = <0>, <0>, <800000000>;
fifo-depth = <64>;
status = "disabled";
};
hsi2c_0: hsi2c@12da0000 {
compatible = "samsung,exynos5260-hsi2c";
reg = <0x12DA0000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_hs_bus>;
clocks = <&clock_peri PERI_CLK_HSIC0>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_1: hsi2c@12db0000 {
compatible = "samsung,exynos5260-hsi2c";
reg = <0x12DB0000 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_hs_bus>;
clocks = <&clock_peri PERI_CLK_HSIC1>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_2: hsi2c@12dc0000 {
compatible = "samsung,exynos5260-hsi2c";
reg = <0x12DC0000 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_hs_bus>;
clocks = <&clock_peri PERI_CLK_HSIC2>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_3: hsi2c@12dd0000 {
compatible = "samsung,exynos5260-hsi2c";
reg = <0x12DD0000 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_hs_bus>;
clocks = <&clock_peri PERI_CLK_HSIC3>;
clock-names = "hsi2c";
status = "disabled";
};
};
};

2
arch/arm/boot/dts/exynos5410-smdk5410.dts
View File

@ -19,7 +19,7 @@
};
chosen {
bootargs = "console=ttySAC2,115200";
stdout-path = "serial2:115200n8";
};
fin_pll: xxti {

364
arch/arm/boot/dts/exynos5420-arndale-octa.dts
View File

@ -24,7 +24,7 @@
};
chosen {
bootargs = "console=ttySAC3,115200";
stdout-path = "serial3:115200n8";
};
firmware@2073000 {
@ -51,6 +51,15 @@
};
};
&adc {
vdd-supply = <&ldo4_reg>;
status = "okay";
};
&cci {
status = "disabled";
};
&cpu0 {
cpu-supply = <&buck2_reg>;
};
@ -59,12 +68,268 @@
cpu-supply = <&buck6_reg>;
};
&usbdrd_dwc3_1 {
dr_mode = "host";
&cpu0_thermal {
trips {
cpu0_alert0: cpu-alert-0 {
temperature = <60000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "passive";
};
cpu0_alert1: cpu-alert-1 {
temperature = <80000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu0_alert2: cpu-alert-2 {
temperature = <110000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu0_crit0: cpu-crit-0 {
temperature = <120000>; /* millicelsius */
hysteresis = <0>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
/*
* Reduce the CPU speed by 2 steps, down to: 1600 MHz
* and 1100 MHz.
*/
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
/*
* Reduce the CPU speed down to 1200 MHz big (6 steps)
* and 800 MHz LITTLE (5 steps).
*/
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&cpu0 3 6>,
<&cpu1 3 6>,
<&cpu2 3 6>,
<&cpu3 3 6>,
<&cpu4 3 5>,
<&cpu5 3 5>,
<&cpu6 3 5>,
<&cpu7 3 5>;
};
/*
* Reduce the CPU speed as much as possible, down to 700 MHz
* big (11 steps) and 600 MHz LITTLE (7 steps).
*/
map2 {
trip = <&cpu0_alert2>;
cooling-device = <&cpu0 6 11>,
<&cpu1 6 11>,
<&cpu2 6 11>,
<&cpu3 6 11>,
<&cpu4 5 7>,
<&cpu5 5 7>,
<&cpu6 5 7>,
<&cpu7 5 7>;
};
};
};
&cci {
status = "disabled";
&cpu1_thermal {
trips {
cpu1_alert0: cpu-alert-0 {
temperature = <60000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "passive";
};
cpu1_alert1: cpu-alert-1 {
temperature = <80000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu1_alert2: cpu-alert-2 {
temperature = <110000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu1_crit0: cpu-crit-0 {
temperature = <120000>; /* millicelsius */
hysteresis = <0>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&cpu0 3 6>,
<&cpu1 3 6>,
<&cpu2 3 6>,
<&cpu3 3 6>,
<&cpu4 3 5>,
<&cpu5 3 5>,
<&cpu6 3 5>,
<&cpu7 3 5>;
};
map2 {
trip = <&cpu1_alert2>;
cooling-device = <&cpu0 6 11>,
<&cpu1 6 11>,
<&cpu2 6 11>,
<&cpu3 6 11>,
<&cpu4 5 7>,
<&cpu5 5 7>,
<&cpu6 5 7>,
<&cpu7 5 7>;
};
};
};
&cpu2_thermal {
trips {
cpu2_alert0: cpu-alert-0 {
temperature = <60000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "passive";
};
cpu2_alert1: cpu-alert-1 {
temperature = <80000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu2_alert2: cpu-alert-2 {
temperature = <110000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu2_crit0: cpu-crit-0 {
temperature = <120000>; /* millicelsius */
hysteresis = <0>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&cpu0 3 6>,
<&cpu1 3 6>,
<&cpu2 3 6>,
<&cpu3 3 6>,
<&cpu4 3 5>,
<&cpu5 3 5>,
<&cpu6 3 5>,
<&cpu7 3 5>;
};
map2 {
trip = <&cpu2_alert2>;
cooling-device = <&cpu0 6 11>,
<&cpu1 6 11>,
<&cpu2 6 11>,
<&cpu3 6 11>,
<&cpu4 6 7>,
<&cpu5 6 7>,
<&cpu6 6 7>,
<&cpu7 6 7>;
};
};
};
&cpu3_thermal {
trips {
cpu3_alert0: cpu-alert-0 {
temperature = <60000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "passive";
};
cpu3_alert1: cpu-alert-1 {
temperature = <80000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu3_alert2: cpu-alert-2 {
temperature = <110000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
type = "passive";
};
cpu3_crit0: cpu-crit-0 {
temperature = <120000>; /* millicelsius */
hysteresis = <0>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&cpu0 3 6>,
<&cpu1 3 6>,
<&cpu2 3 6>,
<&cpu3 3 6>,
<&cpu4 3 5>,
<&cpu5 3 5>,
<&cpu6 3 5>,
<&cpu7 3 5>;
};
map2 {
trip = <&cpu3_alert2>;
cooling-device = <&cpu0 6 11>,
<&cpu1 6 11>,
<&cpu2 6 11>,
<&cpu3 6 11>,
<&cpu4 5 7>,
<&cpu5 5 7>,
<&cpu6 5 7>,
<&cpu7 5 7>;
};
};
};
&hdmi {
@ -107,12 +372,19 @@
regulator-name = "PVDD_APIO_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "PVDD_APIO_MMCON_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/*
* Must be always on, even though there is
* a consumer (mmc_0). Otherwise the board
* does not reboot with vendor U-Boot
* (Linaro for Arndale Octa, v2012.07).
*/
regulator-always-on;
};
@ -145,6 +417,7 @@
regulator-name = "PVDD_ABB_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo9_reg: LDO9 {
@ -176,10 +449,17 @@
ldo13_reg: LDO13 {
regulator-name = "PVDD_APIO_MMCOFF_2V8";
regulator-min-microvolt = <2800000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
};
ldo14_reg: LDO14 {
/* Unused */
regulator-name = "PVDD_LDO14";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
};
ldo15_reg: LDO15 {
regulator-name = "PVDD_PERI_2V8";
regulator-min-microvolt = <3300000>;
@ -192,6 +472,13 @@
regulator-max-microvolt = <2200000>;
};
ldo17_reg: LDO17 {
/* Unused */
regulator-name = "PVDD_LDO17";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
};
ldo18_reg: LDO18 {
regulator-name = "PVDD_EMMC_1V8";
regulator-min-microvolt = <1800000>;
@ -216,10 +503,17 @@
regulator-max-microvolt = <1800000>;
};
ldo22_reg: LDO22 {
/* Unused */
regulator-name = "PVDD_LDO22";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2375000>;
};
ldo23_reg: LDO23 {
regulator-name = "PVDD_MIFS_1V1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
@ -229,6 +523,13 @@
regulator-max-microvolt = <2800000>;
};
ldo25_reg: LDO25 {
/* Unused */
regulator-name = "PVDD_LDO25";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
};
ldo26_reg: LDO26 {
regulator-name = "PVDD_CAM0_AF_2V8";
regulator-min-microvolt = <3000000>;
@ -237,8 +538,8 @@
ldo27_reg: LDO27 {
regulator-name = "PVDD_G3DS_1V0";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
};
ldo28_reg: LDO28 {
@ -253,6 +554,13 @@
regulator-max-microvolt = <1800000>;
};
ldo30_reg: LDO30 {
/* Unused */
regulator-name = "PVDD_LDO30";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
};
ldo31_reg: LDO31 {
regulator-name = "PVDD_PERI_1V8";
regulator-min-microvolt = <1800000>;
@ -271,12 +579,33 @@
regulator-max-microvolt = <1800000>;
};
ldo34_reg: LDO34 {
/* Unused */
regulator-name = "PVDD_LDO34";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
};
ldo35_reg: LDO35 {
regulator-name = "PVDD_CAM0_DVDD_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo36_reg: LDO36 {
/* Unused */
regulator-name = "PVDD_LDO36";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
};
ldo37_reg: LDO37 {
/* Unused */
regulator-name = "PVDD_LDO37";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
};
ldo38_reg: LDO38 {
regulator-name = "PVDD_CAM0_AVDD_2V8";
regulator-min-microvolt = <2800000>;
@ -364,7 +693,7 @@
&mmc_0 {
status = "okay";
broken-cd;
non-removable;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
@ -372,22 +701,27 @@
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
vmmc-supply = <&ldo10_reg>;
vqmmc-supply = <&ldo3_reg>;
bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
};
&mmc_2 {
status = "okay";
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr50;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&pinctrl_0 {
@ -404,3 +738,7 @@
clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
clock-names = "rtc", "rtc_src";
};
&usbdrd_dwc3_1 {
dr_mode = "host";
};

3
arch/arm/boot/dts/exynos5420-smdk5420.dts
View File

@ -21,7 +21,8 @@
};
chosen {
bootargs = "console=ttySAC2,115200 init=/linuxrc";
bootargs = "init=/linuxrc";
stdout-path = "serial2:115200n8";
};
fixed-rate-clocks {

2
arch/arm/boot/dts/exynos5420.dtsi
View File

@ -5,7 +5,7 @@
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
* SAMSUNG EXYNOS5420 SoC device nodes are listed in this file.
* EXYNOS5420 based board files can include this file and provide
* values for board specfic bindings.
*/

5
arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
View File

@ -22,11 +22,12 @@
"Headphone Jack", "HPL",
"Headphone Jack", "HPR",
"Headphone Jack", "MICBIAS",
"IN1", "Headphone Jack",
"IN12", "Headphone Jack",
"Speakers", "SPKL",
"Speakers", "SPKR",
"I2S Playback", "Mixer DAI TX",
"HiFi Playback", "Mixer DAI TX";
"HiFi Playback", "Mixer DAI TX",
"Mixer DAI RX", "HiFi Capture";
assigned-clocks = <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,