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drm: rcar-du: Enable configurable DPAD0 routing on Gen3

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All Gen3 SoCs supported so far have a fixed association between DPAD0
and DU channels, which led to hardcoding that association when writing
the corresponding hardware register. The D3 and E3 will break that
mechanism as DPAD0 can be dynamically connected to either DU0 or DU1.

Make DPAD0 routing dynamic on Gen3. To ensure a valid hardware
configuration when the DU starts without the RGB output enabled, DPAD0
is associated at initialization time to the first DU channel that it can
be connected to. This makes no change on Gen2 as all Gen2 SoCs can
connected DPAD0 to DU0, which is the current implicit default value.

As the DPAD0 source is always 0 when a single source is possible on
Gen2, we can also simplify the Gen2 code in the same function to remove
a conditional check.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
This commit is contained in:
Laurent Pinchart 2018-08-22 00:01:07 +03:00
parent b4734f43f3
commit 1f98b2a4fd
2 changed files with 18 additions and 11 deletions
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17
drivers/gpu/drm/rcar-du/rcar_du_group.c
View File

@ -56,8 +56,6 @@ static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
{
struct rcar_du_device *rcdu = rgrp->dev;
unsigned int possible_crtcs =
rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
u32 defr8 = DEFR8_CODE;
if (rcdu->info->gen < 3) {
@ -69,21 +67,18 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
* DU instances that support it.
*/
if (rgrp->index == 0) {
if (possible_crtcs > 1)
defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
if (rgrp->dev->vspd1_sink == 2)
defr8 |= DEFR8_VSCS;
}
} else {
/*
* On Gen3 VSPD routing can't be configured, but DPAD routing
* needs to be set despite having a single option available.
* On Gen3 VSPD routing can't be configured, and DPAD routing
* is set in the group corresponding to the DPAD output (no Gen3
* SoC has multiple DPAD sources belonging to separate groups).
*/
unsigned int rgb_crtc = ffs(possible_crtcs) - 1;
struct rcar_du_crtc *crtc = &rcdu->crtcs[rgb_crtc];
if (crtc->index / 2 == rgrp->index)
defr8 |= DEFR8_DRGBS_DU(crtc->index);
if (rgrp->index == rcdu->dpad0_source / 2)
defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
}
rcar_du_group_write(rgrp, DEFR8, defr8);

12
drivers/gpu/drm/rcar-du/rcar_du_kms.c
View File

@ -544,6 +544,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
struct drm_device *dev = rcdu->ddev;
struct drm_encoder *encoder;
struct drm_fbdev_cma *fbdev;
unsigned int dpad0_sources;
unsigned int num_encoders;
unsigned int num_groups;
unsigned int swindex;
@ -666,6 +667,17 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
encoder->possible_clones = (1 << num_encoders) - 1;
}
/*
* Initialize the default DPAD0 source to the index of the first DU
* channel that can be connected to DPAD0. The exact value doesn't
* matter as it should be overwritten by mode setting for the RGB
* output, but it is nonetheless required to ensure a valid initial
* hardware configuration on Gen3 where DU0 can't always be connected to
* DPAD0.
*/
dpad0_sources = rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
rcdu->dpad0_source = ffs(dpad0_sources) - 1;
drm_mode_config_reset(dev);
drm_kms_helper_poll_init(dev);