renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-21 03:33:59 +08:00
Code

One small bug fix for the imx6qp CAN clk definition that was causing

Browse Source 
failures and division by zeros in the kernel on those devices.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iQIcBAABCAAGBQJXJ9+WAAoJEK0CiJfG5JUl+IMP/i3xp0lfvVNjZXKN/kQRW14u
 4XdnQCtpyUUEUzGqgSVU7mGaRoLIEjsU0YN4Ewwoqs0fd/HkNzwXcDyerI464doo
 Mi6RT38ELYp/CHh0fIIBYYT+uimrD2Micy+p3yrQpk9E6sXG3uBHCsoT/HThh6Yq
 2rAadWIum9uCjQ3FkjaAENupCYVy0Yh8MM3S+ATsUoInw79MubOG13quS0wD1Ib5
 QYWZsb6F8V4AVWJ9jh+CmAf5Mec67XGQ1LLCZNk8cjpOj+XpBw5JNXzCKbsYuZbb
 zzShV5Du/le81aQGir80GgwVwTOdMAm0SOZvTNGfOaS9kDAV8VFbhWBcwApyTJ2e
 ql27zk2nVJ/9JduqrnkH0qfCe+26IhFvx01sUauHfrpV4YtqNvtYH7sCvU/e+IiJ
 fO54hdWdLtvMWGFyOo62aupZ+Hv2sBfKlml/igzFcsKscFm68efWSOvMZb1HBJqL
 1SWSnEWsXj5vt0bFv3Gc5pQsqbNi9GsbZkBpo0X6KTT6pqxVsF0Xjfc2PQiHbOaT
 rTBIaT97Bzk2FCtuKl5cX5S9FrUe8jjb424p/VKTlhFEOQbu4eMhQkJL8qxeRu7e
 u1DH8QBQVs4CyvslNXcDdpda1D2pqjB4dNFUcyPKiQRzt4ujMA8qe+MmDC9Cgv2J
 Nzx0w6pdt3cnnddIkTCK
 =BKj3
 -----END PGP SIGNATURE-----

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fix from Stephen Boyd:
 "One small bug fix for the imx6qp CAN clk definition that was causing
  failures and division by zeros in the kernel on those devices"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: imx6q: fix typo in CAN clock definition
This commit is contained in:
Linus Torvalds 2016-05-03 10:58:29 -07:00
commit 1f6211a4ea
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/imx/clk-imx6q.c
View File

@ -394,7 +394,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
} else {
clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60", base + 0x20, 2, 6);
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);