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ARM: zynq: Add Z-turn board V5

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Adding Z-turn board V5 to resolve the change between:

"Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
"Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031

Changes v1 -> v2: Instead of using new board, the v2 using a common devicetree
for z-turn boards (zynq-zturn-common.dtsi) and for each board a specific DT

Signed-off-by: Alexandre GRIVEAUX <agriveaux@deutnet.info>
Link: https://lore.kernel.org/r/20201126070516.85882-1-agriveaux@deutnet.info
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Alexandre GRIVEAUX 2020-11-26 08:05:16 +01:00 committed by Michal Simek
parent 3650b228f8
commit 1f4079b626
4 changed files with 129 additions and 100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
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@ -1302,6 +1302,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
zynq-zturn-v5.dtb \
zynq-zybo.dtb \
zynq-zybo-z7.dtb
dtb-$(CONFIG_MACH_ARMADA_370) += \

112
arch/arm/boot/dts/zynq-zturn-common.dtsi Normal file
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@ -0,0 +1,112 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
* Copyright (C) 2017 Alexander Graf <agraf@suse.de>
*
* Based on zynq-zed.dts which is:
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
*
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
/ {
compatible = "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
serial1 = &uart0;
mmc0 = &sdhci0;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
usr-led1 {
label = "usr-led1";
gpios = <&gpio0 0x0 0x1>;
default-state = "off";
};
usr-led2 {
label = "usr-led2";
gpios = <&gpio0 0x9 0x1>;
default-state = "off";
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
K1 {
label = "K1";
gpios = <&gpio0 0x32 0x1>;
linux,code = <0x66>;
wakeup-source;
autorepeat;
};
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
};
};
&sdhci0 {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&can0 {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
stlm75@49 {
status = "okay";
compatible = "lm75";
reg = <0x49>;
};
accelerometer@53 {
compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
reg = <0x53>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x1e 0x4>;
};
};

15
arch/arm/boot/dts/zynq-zturn-v5.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "zynq-zturn-common.dtsi"
/ {
model = "Zynq Z-Turn MYIR Board V5";
compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000";
};
&gem0 {
ethernet_phy: ethernet-phy@0 {
reg = <0x3>;
};
};

101
arch/arm/boot/dts/zynq-zturn.dts
View File

@ -1,114 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
* Copyright (C) 2017 Alexander Graf <agraf@suse.de>
*
* Based on zynq-zed.dts which is:
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
*
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
/include/ "zynq-zturn-common.dtsi"
/ {
model = "Zynq Z-Turn MYIR Board";
compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
serial1 = &uart0;
mmc0 = &sdhci0;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
usr-led1 {
label = "usr-led1";
gpios = <&gpio0 0x0 0x1>;
default-state = "off";
};
usr-led2 {
label = "usr-led2";
gpios = <&gpio0 0x9 0x1>;
default-state = "off";
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
K1 {
label = "K1";
gpios = <&gpio0 0x32 0x1>;
linux,code = <0x66>;
wakeup-source;
autorepeat;
};
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
reg = <0x0>;
};
};
&sdhci0 {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&can0 {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
stlm75@49 {
status = "okay";
compatible = "lm75";
reg = <0x49>;
};
accelerometer@53 {
compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
reg = <0x53>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x1e 0x4>;
};
};