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pinctrl: samsung: use raw_spinlock for locking

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This patch converts spin_[lock|unlock] functions of pin bank to
raw_spinlock to support preempt-rt. This can avoid BUG() assertion when
irqchip callbacks are triggerred. Spinlocks can be converted rt_mutex
which is preemptible when we apply preempt-rt patches.

According to "Documentation/driver-api/gpio/driver.rst",

"Realtime considerations: a realtime compliant GPIO driver should not
use spinlock_t or any sleepable APIs (like PM runtime) as part of its
irqchip implementation.

- spinlock_t should be replaced with raw_spinlock_t.[1]
"

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20210121030009.25673-1-chanho61.park@samsung.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Chanho Park 2021-01-21 12:00:09 +09:00 committed by Linus Walleij
parent cd4919105c
commit 1f306ecbe0
4 changed files with 22 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/pinctrl/samsung/pinctrl-exynos.c
View File

@ -58,13 +58,13 @@ static void exynos_irq_mask(struct irq_data *irqd)
unsigned long mask; unsigned long mask;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask); mask = readl(bank->eint_base + reg_mask);
mask |= 1 << irqd->hwirq; mask |= 1 << irqd->hwirq;
writel(mask, bank->eint_base + reg_mask); writel(mask, bank->eint_base + reg_mask);
spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
} }
static void exynos_irq_ack(struct irq_data *irqd) static void exynos_irq_ack(struct irq_data *irqd)
@ -97,13 +97,13 @@ static void exynos_irq_unmask(struct irq_data *irqd)
if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
exynos_irq_ack(irqd); exynos_irq_ack(irqd);
spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask); mask = readl(bank->eint_base + reg_mask);
mask &= ~(1 << irqd->hwirq); mask &= ~(1 << irqd->hwirq);
writel(mask, bank->eint_base + reg_mask); writel(mask, bank->eint_base + reg_mask);
spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
} }
static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
@ -169,14 +169,14 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con); con = readl(bank->pctl_base + reg_con);
con &= ~(mask << shift); con &= ~(mask << shift);
con |= EXYNOS_PIN_FUNC_EINT << shift; con |= EXYNOS_PIN_FUNC_EINT << shift;
writel(con, bank->pctl_base + reg_con); writel(con, bank->pctl_base + reg_con);
spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
return 0; return 0;
} }
@ -192,14 +192,14 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con); con = readl(bank->pctl_base + reg_con);
con &= ~(mask << shift); con &= ~(mask << shift);
con |= EXYNOS_PIN_FUNC_INPUT << shift; con |= EXYNOS_PIN_FUNC_INPUT << shift;
writel(con, bank->pctl_base + reg_con); writel(con, bank->pctl_base + reg_con);
spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
} }

4
drivers/pinctrl/samsung/pinctrl-s3c24xx.c
View File

@ -145,14 +145,14 @@ static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
val = readl(reg); val = readl(reg);
val &= ~(mask << shift); val &= ~(mask << shift);
val |= bank->eint_func << shift; val |= bank->eint_func << shift;
writel(val, reg); writel(val, reg);
spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
} }
static int s3c24xx_eint_type(struct irq_data *data, unsigned int type) static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)

22
drivers/pinctrl/samsung/pinctrl-samsung.c
View File

@ -400,14 +400,14 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
reg += 4; reg += 4;
} }
spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
data &= ~(mask << shift); data &= ~(mask << shift);
data |= func->val << shift; data |= func->val << shift;
writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
} }
/* enable a specified pinmux by writing to registers */ /* enable a specified pinmux by writing to registers */
@ -451,7 +451,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
width = type->fld_width[cfg_type]; width = type->fld_width[cfg_type];
cfg_reg = type->reg_offset[cfg_type]; cfg_reg = type->reg_offset[cfg_type];
spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
mask = (1 << width) - 1; mask = (1 << width) - 1;
shift = pin_offset * width; shift = pin_offset * width;
@ -468,7 +468,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
*config = PINCFG_PACK(cfg_type, data); *config = PINCFG_PACK(cfg_type, data);
} }
spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
return 0; return 0;
} }
@ -561,9 +561,9 @@ static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
struct samsung_pin_bank *bank = gpiochip_get_data(gc); struct samsung_pin_bank *bank = gpiochip_get_data(gc);
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
samsung_gpio_set_value(gc, offset, value); samsung_gpio_set_value(gc, offset, value);
spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
} }
/* gpiolib gpio_get callback function */ /* gpiolib gpio_get callback function */
@ -626,9 +626,9 @@ static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
unsigned long flags; unsigned long flags;
int ret; int ret;
spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
ret = samsung_gpio_set_direction(gc, offset, true); ret = samsung_gpio_set_direction(gc, offset, true);
spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
return ret; return ret;
} }
@ -640,10 +640,10 @@ static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
unsigned long flags; unsigned long flags;
int ret; int ret;
spin_lock_irqsave(&bank->slock, flags); raw_spin_lock_irqsave(&bank->slock, flags);
samsung_gpio_set_value(gc, offset, value); samsung_gpio_set_value(gc, offset, value);
ret = samsung_gpio_set_direction(gc, offset, false); ret = samsung_gpio_set_direction(gc, offset, false);
spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
return ret; return ret;
} }
@ -1057,7 +1057,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
bank->eint_offset = bdata->eint_offset; bank->eint_offset = bdata->eint_offset;
bank->name = bdata->name; bank->name = bdata->name;
spin_lock_init(&bank->slock); raw_spin_lock_init(&bank->slock);
bank->drvdata = d; bank->drvdata = d;
bank->pin_base = d->nr_pins; bank->pin_base = d->nr_pins;
d->nr_pins += bank->nr_pins; d->nr_pins += bank->nr_pins;

2
drivers/pinctrl/samsung/pinctrl-samsung.h
View File

@ -171,7 +171,7 @@ struct samsung_pin_bank {
struct gpio_chip gpio_chip; struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange; struct pinctrl_gpio_range grange;
struct exynos_irq_chip *irq_chip; struct exynos_irq_chip *irq_chip;
spinlock_t slock; raw_spinlock_t slock;
u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
}; };