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x86, UV: Fix NMI handler for UV platforms
This fixes problems seen on UV systems handling NMIs from the node controller. I isolated the "dazed..." messages that I saw earlier to a bug in the BMC on our platform. It was sending NMIs w/o properly setting a register that indicated the source of NMI. So rather than _assuming_ any unhandled NMI came from the UV system maintenance console (SMC), add a check to verify that the SMC actually sent the NMI. Signed-off-by: Jack Steiner <steiner@sgi.com> Cc: gorcunov@gmail.com Cc: dzickus@redhat.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -398,6 +398,8 @@ struct uv_blade_info {
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unsigned short nr_online_cpus;
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unsigned short pnode;
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short memory_nid;
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spinlock_t nmi_lock;
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unsigned long nmi_count;
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};
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extern struct uv_blade_info *uv_blade_info;
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extern short *uv_node_to_blade;
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@ -5,7 +5,7 @@
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*
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* SGI UV MMR definitions
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*
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* Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
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* Copyright (C) 2007-2011 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_X86_UV_UV_MMRS_H
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@ -1099,5 +1099,19 @@ union uvh_rtc1_int_config_u {
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} s;
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};
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/* ========================================================================= */
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/* UVH_SCRATCH5 */
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/* ========================================================================= */
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#define UVH_SCRATCH5 0x2d0200UL
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#define UVH_SCRATCH5_32 0x00778
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#define UVH_SCRATCH5_SCRATCH5_SHFT 0
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#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
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union uvh_scratch5_u {
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unsigned long v;
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struct uvh_scratch5_s {
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unsigned long scratch5 : 64; /* RW, W1CS */
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} s;
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};
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#endif /* __ASM_UV_MMRS_X86_H__ */
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@ -37,6 +37,13 @@
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#include <asm/smp.h>
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#include <asm/x86_init.h>
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#include <asm/emergency-restart.h>
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#include <asm/nmi.h>
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/* BMC sets a bit this MMR non-zero before sending an NMI */
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#define UVH_NMI_MMR UVH_SCRATCH5
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#define UVH_NMI_MMR_CLEAR (UVH_NMI_MMR + 8)
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#define UV_NMI_PENDING_MASK (1UL << 63)
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DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count);
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DEFINE_PER_CPU(int, x2apic_extra_bits);
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@ -642,18 +649,46 @@ void __cpuinit uv_cpu_init(void)
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*/
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int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
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{
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unsigned long real_uv_nmi;
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int bid;
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if (reason != DIE_NMIUNKNOWN)
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return NOTIFY_OK;
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if (in_crash_kexec)
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/* do nothing if entering the crash kernel */
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return NOTIFY_OK;
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/*
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* Use a lock so only one cpu prints at a time
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* to prevent intermixed output.
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* Each blade has an MMR that indicates when an NMI has been sent
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* to cpus on the blade. If an NMI is detected, atomically
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* clear the MMR and update a per-blade NMI count used to
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* cause each cpu on the blade to notice a new NMI.
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*/
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bid = uv_numa_blade_id();
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real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
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if (unlikely(real_uv_nmi)) {
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spin_lock(&uv_blade_info[bid].nmi_lock);
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real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
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if (real_uv_nmi) {
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uv_blade_info[bid].nmi_count++;
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uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK);
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}
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spin_unlock(&uv_blade_info[bid].nmi_lock);
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}
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if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count))
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return NOTIFY_DONE;
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__get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count;
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/*
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* Use a lock so only one cpu prints at a time.
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* This prevents intermixed output.
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*/
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spin_lock(&uv_nmi_lock);
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pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
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pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id());
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dump_stack();
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spin_unlock(&uv_nmi_lock);
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@ -661,7 +696,8 @@ int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
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}
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static struct notifier_block uv_dump_stack_nmi_nb = {
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.notifier_call = uv_handle_nmi
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.notifier_call = uv_handle_nmi,
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.priority = NMI_LOCAL_LOW_PRIOR - 1,
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};
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void uv_register_nmi_notifier(void)
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@ -720,8 +756,9 @@ void __init uv_system_init(void)
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printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
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bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
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uv_blade_info = kmalloc(bytes, GFP_KERNEL);
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uv_blade_info = kzalloc(bytes, GFP_KERNEL);
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BUG_ON(!uv_blade_info);
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for (blade = 0; blade < uv_num_possible_blades(); blade++)
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uv_blade_info[blade].memory_nid = -1;
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@ -747,6 +784,7 @@ void __init uv_system_init(void)
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uv_blade_info[blade].pnode = pnode;
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uv_blade_info[blade].nr_possible_cpus = 0;
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uv_blade_info[blade].nr_online_cpus = 0;
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spin_lock_init(&uv_blade_info[blade].nmi_lock);
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max_pnode = max(pnode, max_pnode);
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blade++;
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}
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