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drm/i915: Disable AsyncFlip performance optimisations
This is a required workarounds for all products, especially on gen6+ where it causes the command streamer to fail to parse instructions following a WAIT_FOR_EVENT. We use WAIT_FOR_EVENT for synchronising between the GPU and the display engines, and so this bit being unset may cause hangs. References: https://bugzilla.kernel.org/show_bug.cgi?id=52311 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -533,6 +533,7 @@
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#define MI_MODE 0x0209c
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# define VS_TIMER_DISPATCH (1 << 6)
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# define MI_FLUSH_ENABLE (1 << 12)
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# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
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#define GEN6_GT_MODE 0x20d0
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#define GEN6_GT_MODE_HI (1 << 9)
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@ -505,13 +505,20 @@ static int init_render_ring(struct intel_ring_buffer *ring)
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret = init_ring_common(ring);
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if (INTEL_INFO(dev)->gen > 3) {
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if (INTEL_INFO(dev)->gen > 3)
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I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
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if (IS_GEN7(dev))
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I915_WRITE(GFX_MODE_GEN7,
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_MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
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_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
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}
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/* We need to disable the AsyncFlip performance optimisations in order
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* to use MI_WAIT_FOR_EVENT within the CS. It should already be
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* programmed to '1' on all products.
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*/
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if (INTEL_INFO(dev)->gen >= 6)
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I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
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if (IS_GEN7(dev))
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I915_WRITE(GFX_MODE_GEN7,
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_MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
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_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
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if (INTEL_INFO(dev)->gen >= 5) {
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ret = init_pipe_control(ring);
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