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Revert "drm/i915/color: Extract icl_read_luts()"
This reverts commit84af764918. This is causing problems with the display, displays are all bright colors. Fixes:84af764918("drm/i915/color: Extract icl_read_luts()") Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190924135820.11850-1-swati2.sharma@intel.com
This commit is contained in:
Swati Sharma
Jani Nikula
parent
b1da91c9dd
commit
1b8588741f
@ -1420,9 +1420,6 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
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static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
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{
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if (!crtc_state->gamma_enable)
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return 0;
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switch (crtc_state->gamma_mode) {
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case GAMMA_MODE_MODE_8BIT:
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return 8;
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@ -1436,9 +1433,6 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
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static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
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{
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if (!crtc_state->gamma_enable)
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return 0;
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if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
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return 0;
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@ -1455,9 +1449,6 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
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static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
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{
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if (!crtc_state->gamma_enable)
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return 0;
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if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
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return 10;
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else
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@ -1466,9 +1457,6 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
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static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
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{
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if (!crtc_state->gamma_enable)
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return 0;
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switch (crtc_state->gamma_mode) {
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case GAMMA_MODE_MODE_8BIT:
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return 8;
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@ -1480,39 +1468,21 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
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}
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}
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static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
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{
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if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
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return 0;
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switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
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case GAMMA_MODE_MODE_8BIT:
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return 8;
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case GAMMA_MODE_MODE_10BIT:
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return 10;
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case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
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return 16;
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default:
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MISSING_CASE(crtc_state->gamma_mode);
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return 0;
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}
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}
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int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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if (!crtc_state->gamma_enable)
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return 0;
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if (HAS_GMCH(dev_priv)) {
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if (IS_CHERRYVIEW(dev_priv))
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return chv_gamma_precision(crtc_state);
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else
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return i9xx_gamma_precision(crtc_state);
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} else {
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if (INTEL_GEN(dev_priv) >= 11)
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return icl_gamma_precision(crtc_state);
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else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
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if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
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return glk_gamma_precision(crtc_state);
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else if (IS_IRONLAKE(dev_priv))
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return ilk_gamma_precision(crtc_state);
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@ -1543,20 +1513,6 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
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return true;
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}
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static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
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struct drm_color_lut *lut2,
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int lut_size, u32 err)
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{
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int i;
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for (i = 0; i < 9; i++) {
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if (!err_check(&lut1[i], &lut2[i], err))
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return false;
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}
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return true;
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}
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bool intel_color_lut_equal(struct drm_property_blob *blob1,
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struct drm_property_blob *blob2,
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u32 gamma_mode, u32 bit_precision)
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@ -1575,8 +1531,16 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
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lut_size2 = drm_color_lut_size(blob2);
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/* check sw and hw lut size */
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if (lut_size1 != lut_size2)
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return false;
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switch (gamma_mode) {
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case GAMMA_MODE_MODE_8BIT:
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case GAMMA_MODE_MODE_10BIT:
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if (lut_size1 != lut_size2)
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return false;
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break;
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default:
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MISSING_CASE(gamma_mode);
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return false;
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}
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lut1 = blob1->data;
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lut2 = blob2->data;
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@ -1584,18 +1548,13 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
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err = 0xffff >> bit_precision;
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/* check sw and hw lut entry to be equal */
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switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
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switch (gamma_mode) {
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case GAMMA_MODE_MODE_8BIT:
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case GAMMA_MODE_MODE_10BIT:
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if (!intel_color_lut_entry_equal(lut1, lut2,
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lut_size2, err))
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return false;
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break;
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case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
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if (!intel_color_lut_entry_multi_equal(lut1, lut2,
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lut_size2, err))
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return false;
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break;
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default:
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MISSING_CASE(gamma_mode);
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return false;
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@ -1835,60 +1794,6 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
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crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
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}
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static struct drm_property_blob *
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icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
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enum pipe pipe = crtc->pipe;
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struct drm_property_blob *blob;
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struct drm_color_lut *blob_data;
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u32 i, val1, val2;
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blob = drm_property_create_blob(&dev_priv->drm,
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sizeof(struct drm_color_lut) * lut_size,
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NULL);
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if (IS_ERR(blob))
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return NULL;
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blob_data = blob->data;
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I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
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for (i = 0; i < 9; i++) {
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val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
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val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
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blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
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REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
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blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
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REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
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blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
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REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
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}
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/*
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* FIXME readouts from PAL_PREC_DATA register aren't giving correct values
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* in the case of fine and coarse segments. Restricting readouts only for
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* super fine segment as of now.
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*/
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return blob;
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}
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static void icl_read_luts(struct intel_crtc_state *crtc_state)
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{
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if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
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GAMMA_MODE_MODE_8BIT)
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crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
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else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
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GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
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crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state);
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else
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crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
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}
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void intel_color_init(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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@ -1932,7 +1837,6 @@ void intel_color_init(struct intel_crtc *crtc)
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if (INTEL_GEN(dev_priv) >= 11) {
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dev_priv->display.load_luts = icl_load_luts;
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dev_priv->display.read_luts = icl_read_luts;
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} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
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dev_priv->display.load_luts = glk_load_luts;
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dev_priv->display.read_luts = glk_read_luts;
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@ -10575,12 +10575,6 @@ enum skl_power_gate {
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#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
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#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
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#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
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#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
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#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
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#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
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#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
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#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
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#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
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_PAL_PREC_MULTI_SEG_INDEX_A, \
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